List based method and apparatus for selective and rapid...

Details List based method and apparatus for selective and rapid... List based method and apparatus for selective and rapid...

2005-11-15

2005-11-15

McLean-Mayo, Kimberly (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S144000, C711S118000, C711S141000

Reexamination Certificate

active

06965970

ABSTRACT:
An apparatus and a method for rapidly flushing a cache memory device, including a list structure to track changes in a cache, which may be implemented on the processor die separate from the cache memory. The list structure allows for access to a relatively small store of data to determine whether or not a cache entry needs to be written to the main memory. Choosing the format of the list structure, allows one to make tradeoffs between area needed on a chip and the amount of efficiency in the cache flushing process.

REFERENCES:
patent: 5724550 (1998-03-01), Stevens
patent: 5761501 (1998-06-01), Lubbers et al.
patent: 5860100 (1999-01-01), Feiste et al.
patent: 5860105 (1999-01-01), McDermott
patent: 6058456 (2000-05-01), Arimilli
patent: 6122711 (2000-09-01), Mackenthun et al.
patent: 6272033 (2001-08-01), Watt
patent: 6418515 (2002-07-01), Kurosawa
patent: 6460122 (2002-10-01), Otterness
patent: 6470422 (2002-10-01), Cai et al.
patent: 6490657 (2002-12-01), Masubuchi

Affiliated with

Also associated with

Rating

List based method and apparatus for selective and rapid... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with List based method and apparatus for selective and rapid..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and List based method and apparatus for selective and rapid... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3471255