Computer graphics processing and selective visual display system – Display driving control circuitry – Adjusting display pixel size or pixels per given area
Reexamination Certificate
1998-03-19
2002-09-10
Hjerpe, Richard (Department: 2774)
Computer graphics processing and selective visual display system
Display driving control circuitry
Adjusting display pixel size or pixels per given area
C345S098000
Reexamination Certificate
active
06448976
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display apparatus and its liquid crystal drive circuit which enables a liquid crystal panel to display graphic data even with a resolution different from a resolution of the liquid crystal panel.
2. Description of Related Art
As a conventional liquid crystal drive circuit, there is a TFT liquid crystal data driver HD66330T which is 192-channel 64-pixel×6-bit, described in pages 952-954, Hitachi LCD controller/driver LSI data book (Hitachi, Ltd., published March 1994).
FIG. 13
is a schematic illustration showing an internal structure of HD66330T. An operation of the conventional liquid crystal driver circuit will now be explained with reference to FIG.
13
.
In
FIG. 13
,
1301
indicates a latch address control circuit,
1302
indicates a latch circuit (
1
),
1303
indicates a latch circuit (
2
),
1304
indicates a liquid crystal applied voltage generation circuit,
1305
indicates a clock for latching input display data,
1306
indicates a line clock with a period of one line,
1307
indicates the input display data,
1308
indicates latch signals,
1309
indicates latch circuit (
1
) output data,
1310
indicates latch circuit (
2
) output data,
1311
indicates base voltages for providing bases of the liquid crystal apply voltages,
1312
indicates liquid crystal applied voltage outputs, and
1313
indicates a chip enable signal.
First, the latch address control circuit
1301
generates the latch signals
1308
for latching the input display data
1307
successively, the input display data
1307
being inputted in synchronization with the clock
1305
. The latch circuit (
1
)
1302
latches the input display data
1307
of 3-channel 1 pixel×6-bit successively in accordance with the latch signals
1308
. Data of
192
-channel 64-pixel×6-bit latched by the latch circuit (
1
)
1302
are then latched by the latch circuit (
2
)
1303
in synchronization with the line clock
1306
. The data latched by the latch circuit (
2
)
1303
are decoded pixel by pixel. The applied voltages are generated according to the decoding results, and are outputted from the liquid crystal apply voltage generation circuit
1304
.
FIG. 14
schematically illustrates a liquid crystal display apparatus with HD66330T, the conventional liquid crystal driver circuit. The prior art will now be explained with reference to FIG.
14
.
In
FIG. 14
,
1401
-U indicates an upper part of a liquid crystal drive circuit comprising an array of the conventional liquid crystal drive circuits,
1401
-L indicates a lower part of a liquid crystal drive circuit comprising an array of the conventional liquid crystal drive circuits,
1402
indicates a scanning driver,
1403
indicates a controller ,
1404
indicates a liquid crystal display panel,
1405
indicates input RGB display data to be inputted to the liquid crystal display apparatus ,
1406
indicates a dot clock,
1407
indicates a horizontal sync signal,
1408
indicates a vertical sync signal,
1409
indicates a display timing signal,
1410
-U indicates upper display data,
1410
-L indicates lower display data,
1411
-U indicates an upper clock generated by halving a frequency of the dot clock,
1411
-L indicates a lower clock generated by halving a frequency of the dot clock,
1412
indicates the first line marker indicating a start of the scanning operation and
1413
indicates a shift clock with the same frequency as that of the horizontal sync signal.
As shown in
FIG. 14
, the controller
1403
divides the dot clock
1406
into one half of the original frequency, and outputs, the upper clock
1411
-U and the lower clock
1411
-L. The controller
1403
also selects the input display data
1405
having every RGB data of odd and even number pixels, and outputs the R data of the odd number pixels, the B data of the odd number pixels and the G data of the even number pixels as the upper display data
1410
-U, and outputs the G data of the odd number pixels, the R data of the even number pixels and the B data of the even number pixels as the lower display data
1410
-L.
The liquid crystal drive circuits
1401
-U and
1401
-L latch the display data
1410
-U and
1410
-L outputted from the controller
1403
at trailing edges of the clocks
1411
-U and
1411
-L, and output the liquid crystal applied voltages to every pixel at the leading edge of the line clock
1306
.
The scanning driver
1402
selects the lines in accordance with the first line marker
1412
and the shift clock
1413
to realize a display on the liquid crystal panel. Accordingly, a train of the input display data
1405
is displayed as they are on the liquid crystal panel. The input display data
1405
usually have the same resolution as that of the liquid crystal panel
1404
, and are displayed over the whole display area of the liquid crystal panel.
SUMMARY OF THE INVENTION
In the prior art described above, the display could not be carried out properly when the display data with a lower resolution than that of the liquid crystal panel are to be inputted.
FIG. 15
is a schematic illustration of a case where the display data with a lower resolution than that of the liquid crystal panel are to be inputted.
When the display data
1405
with a lower resolution than that of the liquid crystal panel are inputted, no data is latched at the liquid crystal drive circuits located at right ends of the liquid crystal drive circuits
1401
-U and
1401
-L because there are less display data in the lateral direction and effective display area for the input display data
1405
is displayed at the upper left. A position of such a display may not be well balanced with respect to the liquid crystal panel
1404
. Furthermore, the data display area in such a display would be smaller compared to the total display area of the liquid crystal panel
1404
. Accordingly, a large display area may not be utilized effectively due to the increase of the ineffective display area if the liquid crystal panel of a higher resolution is used. These are presented as problems.
Normally, there are data in the ineffective display interval which occurs between the effective display interval and a pulse of the line clock
306
. As shown in
FIG. 15
, the problems of not being able to latch the data in the right end side of the driver as described above may also be observed when the total number of the pixels in one line is less than a number of pixels in the lateral direction of the liquid crystal panel
1404
, even if the data during the ineffective display interval are additionally used.
The object of the present invention is to provide a liquid crystal drive circuit enabling a decrease in the ineffective display area by expanding the display data, and to display the display data in the middle part of the liquid crystal panel even when the display data with a lower resolution than that of the liquid crystal panel are to be inputted.
General features of typical embodiments of the inventions disclosed in the present application will now be explained as follows.
The present invention in the first embodiment provides a liquid crystal drive circuit comprising: a latch address control circuit for generating a latch signal or a plurality of latch signals in parallel according to a parallel latch number control signal specifying a number of the display data to be latched in parallel; a data control circuit for controlling display data to be latched in parallel according to the control signal; a the-first hold circuit for latching the display data controlled by the data control circuit for an amount of output data lines according to the latch signals,. and holding the latched data; a second hold circuit for latching the display data held in the first hold circuit in parallel for an amount of the output data lines according to a horizontal sync signal, and holding the latched data; and a gray scale voltage output circuit for selecting gray scale voltages generated by dividing base voltages in accordance with the display data h
Furuhashi Tsutomu
Higa Atsuhiro
Kurihara Hiroshi
Nakamura Masashi
Nitta Hiroyuki
Dinh Duc Q.
Hitachi , Ltd.
Hjerpe Richard
Mattingly, Stanger & Malur
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