Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-02-10
2003-09-30
Saras, Steven (Department: 2675)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S100000, C345S096000
Reexamination Certificate
active
06628261
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a drive circuit for a liquid crystal display apparatus of active matrix type, or more in particular to a liquid crystal display apparatus having a drive circuit formed on the same substrate as an active matrix substrate.
The liquid crystal display apparatus of active matrix type comprises a display unit formed with a transistor at each intersection of a plurality of signal lines and scanning lines arranged orthogonally to each other and a drive circuit unit for controlling the voltages of the signal lines and the scanning lines. The transistors used for the display unit include an amorphous silicon (a-Si) thin-film transistor (TFT), a poly-silicon (p-Si) thin film transistor, and a single-crystal silicon MOS (Metal-Oxide Semiconductor) transistor. The a-Si TFT is formed on a glass substrate, and as a drive circuit thereof, a single-crystal silicon integrated circuit is mounted externally. The p-Si TFT is either a high-temperature p-Si TFT formed on a quartz substrate or a low-temperature p-Si TFT formed on a glass substrate. The drive circuit for the liquid crystal display apparatus using the p-Si TFT is formed on the same substrate as the display unit. The amorphous silicon TFT or the low-temperature p-Si TFT formed on the glass substrate can realize a large size screen, while a quartz substrate or a single-crystal silicon substrate is limited to a screen of small or medium size.
The configuration and the operation of the liquid crystal display apparatus of active matrix type will be described in more detail.
Each of the transistors of the display unit has a gate connected to a scanning line, a drain to a signal line and a source to a display electrode. Another substrate formed with a transparent electrode on one surface thereof is arranged in opposed relation to the display electrode, and the liquid crystal is held between the display electrode and the opposed substrate. Normally, the display electrode is connected with a holding capacitor, and therefore the holding capacitor and a liquid crystal capacitor are connected in parallel to the source electrode. When the gate electrode enters a select mode, the transistor turns on, and writes the video signal from the signal line into the liquid crystal capacitor and the holding capacitor. When the gate electrode turns to a non-select mode, on the other hand, the transistor comes to assume a high impedance, and holds the video signal written in the liquid crystal.
The drive circuit unit includes a scanning circuit for controlling the voltage on the scanning line and a signal circuit for controlling the voltage on the signal line. The scanning circuit applies a scan pulse once per frame time to each scanning line. Normally, this pulse timing is differentiated sequentially downward of the panel. One frame time of {fraction (1/60)} second is often used. A panel having a typical pixel array of 1024×768 dots is scanned 768 times per frame time, and therefore the time width of the scan pulse is about 20 &mgr;s. This scanning circuit is normally configured with a shift register which has an operating speed of about 50 kHz.
On the other hand, the signal circuit supplies each signal line with a liquid crystal drive voltage corresponding to the pixels for one line applied with the scan pulse. In the selected pixels applied with the scan pulse, the voltage of the gate electrode of the transistor connected to the scanning line increases and turns on the transistor. In the process, the liquid crystal drive voltage is applied to the liquid crystal through the drain and the source of the transistor from the signal line, thereby charging the pixel capacitor including the liquid crystal capacitor and the holding capacitor. By repeating this process of operation, a voltage corresponding to the repetitive video signal is applied to the pixel capacitors over the whole surface of the panel for each frame time.
In the case of analog system, the signal circuit for driving the signal line is configured with a shift register and a sample/hold circuit. The shift register generates a timing for the sample/hold circuit corresponding to each pixel. In the sample/hold circuit, the video signal corresponding to each pixel is sampled at this timing, and the liquid crystal drive voltage is supplied to each signal line. This driving method can be realized with a simple circuit configuration including a shift register for generating a timing and a sample/hold circuit for sampling the video signal. This driving method, therefore, is used primarily for a liquid crystal display panel integrated with a drive circuit.
In the aforementioned pixel configuration, the shift register of the signal circuit generates 1024 timing pulses with a time width of the scan pulse of the scanning circuit. As a result, the time interval of the timings of the shift register is not more than 20 ns, and therefore this shift register requires an operating speed of not less than 50 MHz. The sample/hold circuit is required to sample the video signal with this short timing. In the liquid crystal display apparatus integrated with the drive circuit, the sampling time is lengthened by dividing the video signal into a plurality of portions and inputting them in parallel. For this purpose, a signal conversion circuit is required in which a high-speed video signal is split into a plurality of video signals by sampling and the signals thus split are amplified and converted into an alternating current.
In the digital system, on the other hand, the signal circuit for driving the signal lines includes a shift register, a two-stage latch circuit, and a digital-to-analog converter (hereinafter referred to as D/A converter). The video signals sequentially input in digital form are stored in the latch circuit corresponding to each signal line by the shift register and the two-stage latch circuit. The D/A converter converts this data into an analog voltage and thus supplies the liquid crystal drive voltage to each signal line.
The number of bits for the latch circuit and the D/A converter of this system is determined by the gradation to be displayed, and is 8 in the case where 256 tones of each color is required for full-color display. In the pixel configuration described above, a latch circuit of 16384 bits (8 bits×2×1024) and 1024 8-bit D/A converters are required. In the D/A converter for each signal line, the reference voltage is selected by switch in order to reduce variations. In this digital system, the video signal is a digital signal, and therefore the S/N (signal-to-noise) ratio can be prevented from deteriorating at the time of signal transmission.
In both the analog system and the digital system described above, the signal line is required to be driven with an accurate voltage for displaying a high-quality image. The signal line is a capacitive load, the capacitance of which is determined by the capacitance between the drain and gate of the transistor making up the display unit, the crossing capacitance between the signal line and the scanning line and the capacitance between the signal line and the transparent electrode of the opposed substrate. The capacitance of the capacitive load of the signal line, therefore, increases with the size of the display unit and the number of pixels making it up. In the a-Si TFT capable of realizing a large-sized display apparatus, therefore, a buffer amplifier for driving the capacitive load of the signal line is used as an external drive circuit configured with an integrated circuit. With this drive technique using the buffer amplifier, the offset voltage is required to be reduced with the capacitance drivability. This can be achieved by either a method using a differential amplifier circuit or a method using a source-follower amplifier circuit.
A method using a differential amplifier circuit is described, for example, in JP-A-5-297830. This method is an application to a signal line drive circuit of analog type and performs the function of a sample/hold circuit at the same time. This
Kawachi Genshiro
Mikami Yoshiro
Ohkubo Tatsuya
Sato Hideo
Shimomura Shigeo
Antonelli Terry Stout & Kraus LLP
Awad Amr
Saras Steven
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