Liquid crystal display having different common voltages

Details Liquid crystal display having different common voltages Liquid crystal display having different common voltages

1998-07-22

2001-05-08

Chow, Dennis-Doon (Department: 2775)

Computer graphics processing and selective visual display system

Plural physical display element control system

Display elements arranged in matrix

C345S090000, C345S092000, C345S095000, C349S033000, C349S056000

Reexamination Certificate

active

06229510

ABSTRACT:

BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a liquid crystal display (LCD). More particularly, this invention relates to a thin film transistor (TFT) LCD having different common voltages.
(b) Description of the Related Art
A TFT-LCD is a display device for displaying image by applying an electric field to a liquid crystal which has a dielectric anisotropy and is interposed between a pair of panels facing each other, and by varying the field intensity to vary the transmittance of light.
The TFT-LCD has a substrate where a plurality of gate lines and a plurality of data lines are formed thereon. The gate lines and the data lines intersect each other and form a plurality of pixels which are surrounded by the gate and data lines. The pixel includes a TFT.
FIG. 1
shows an equivalent circuit of the pixel in the TFT-LCD.
As shown in
FIG. 1
, the TFT-LCD has a TFT having a gate electrode g, a source electrode s and a drain electrode d connected each to a gate line Gn, a data line Dm and a pixel electrode P. The liquid crystal is interposed between the pixel electrode P and the common electrode Com and is represented with the liquid crystal capacitor Clc. A storage capacitor Cst is formed between the pixel electrode P and a previous gate line Gn-
1
and a parasitic Cgd is formed between the gate electrode g and the drain electrode d, due to the misalignment of patterns. The TFT-LCD mentioned above operates as follows.
First, the TFT
10
is turned on by applying a gate-on voltage to the gate electrode connected to the gate line Gn and then a data voltage representing the image signal is applied to the source electrode s and the data voltage is applied the drain electrode d through the TFT
10
. Consequentially, the data voltage is applied to the liquid crystal capacitor Clc and the storage capacitor Cst via the pixel electrode P respectively and therefore the electric field is generated by a voltage difference between the pixel electrode P and the common electrode Com. At this time, if the same-directional electric field is continuously applied to the liquid crystal, the liquid crystal is degraded. For this reason, in the LCD panel, for the purpose of preventing the degradation of the liquid crystal, the image signal is driven by alternately changing plus and minus in comparison with the common voltage. The driving method like this is called as inversion driving method.
Meanwhile, the voltage applied to the liquid crystal capacitor Clc and the storage capacitor Cst while the TFT turns on, should be maintained till the TFT turns off. However, due to the parasitic capacitance Cgd between the gate electrode and the drain electrode, the voltage applied to the pixel electrode happens to be distorted. The distorted voltage like this is called as a kick-back voltage and the kick-back voltage is got by following formula.
Δ
⁢
 
⁢
V
=
Cgd
Cgd
+
Cst
+
Clc
×
Δ
⁢
 
⁢
Vg
(
1
)
Herein, &Dgr;Vg means a changing amount of the gate voltage.
The voltage distortion, irrespective of the polarity of the data voltage, always lowers the voltage of the pixel electrode as shown in FIG.
2
.
In
FIG. 2
, Vg, Vd and Vp represent the gate voltage, the data voltage and a voltage of the pixel electrode respectively. Vcom and &Dgr;V indicate a voltage of the common electrode (common voltage) and the kick-back voltage respectively.
As shown in
FIG. 2
with dot lines, in an ideal TFT-LCD, the data voltage Vd applied to the pixel electrode while the gate voltage Vg is in ‘on’ state, is maintained even if the gate voltage turns off. However, in a real TFT-LCD, as shown in
FIG. 2
with lines, the voltage of the pixel electrode is lowered by the kick-back voltage in a point where the gate voltage changes due to the kick-back voltage.
On the other hand, a root mean square (RMS) electric field applied to the liquid crystal is determined by the area between the pixel voltage Vd and the common voltage Vcom. Therefore, if the LCD is driven by the inversion driving method, the common voltage level needs to be adjusted so that the area of the pixel voltage for the common voltage is symmetric. This is because that if the area of the pixel voltage Vp for the common voltage Vcom is not symmetric, the amount of the pixel voltage charged in each pixel becomes different by a frame, and therefore whenever the pixel voltage is inverse, it happens the flicker. Consequentially, in a conventional manner, a fixed common voltage being symmetric with the area of the pixel voltage was applied to the common electrode.
However, even if the fixed common voltage is applied to the common electrode for the purpose of preventing the flicker, it happens the flicker yet for the following reason.
Generally, there are a resistance and a parasitic capacitance in the gate line and the data line as shown in FIG.
3
.
Though a plurality of the gate lines and a plurality of the data lines are actually formed on the LCD panel
20
, only a gate line Gi and a data line Dm are shown for convenience in FIG.
3
.
Since the gate line Gi and the data line Dm include a resistance Rg, Rd and the parasitic capacitance Cg, Cd, the gate voltage and the data voltage are delayed by a time constant determined by a multiplication of the resistance and the parasitic capacitance. The voltage delay becomes larger as the size of the LCD panel increases.
FIG. 4
shows the measuring value of the gate voltage Vg delayed according to the length of the gate line. Vg
1
and Vg
2
indicate the gate voltage measured in the close point A and the far away point B of the gate line from the input terminal of the gate voltage respectively.
As shown in
FIG. 4
, the changing amount of the gate voltage becomes smaller as it becomes farther away from the input terminal of the gate voltage, that is, the delay of the gate voltage becomes larger. Accordingly, as can be known in Formula 1, the kick-back voltage &Dgr;V becomes smaller.
Since the common voltage is not maintained to a mid value of the pixel voltage if the common voltage is applied constantly, the voltage value charged in the pixel by the frame becomes different and it cause to happen the flicker. The phenomena of the flicker becomes more serious as the screen of the LCD becomes larger.
Meanwhile, since the data voltage as same as the gate voltage is delayed due to the resistance Rd and the parasitic capacitance Cd, the waveform of the data voltage applied to the pixel electrode is distorted and accordingly the charging amount of the pixel voltage of the close point C and the far away point D from the input terminal of the data voltage becomes different.
FIG. 5
shows the difference in the charging amount of the pixel voltage due to the delay of the data voltage.
As shown in
FIG. 5
, if the data voltage is applied to the data line Dm, the voltage Vd
1
of the close point C from the input terminal becomes the data voltage Vd without a signal delay but the voltage Vd
2
of the far away point D from the input terminal does not become the data voltage Vd till it is delayed by the time constant &tgr;. Therefore, as shown with a hatched region in
FIG. 5
, the data voltage is less charged in the pixel of the D point than in the pixel of the C point by the &Dgr;Vd.
The difference of the charging amount affects a brightness of an image and therefore degrades the image quality. This problem becomes more serious as the panel of the LCD becomes larger.
SUMMARY OF THE INVENTION
An object of the invention is to overcome the above described problems. Another object of the invention is to prevent the flicker due to the gate voltage delay and the ununiformity of the image due to the data voltage delay.


REFERENCES:
patent: 5774099 (1998-06-01), Iwasaki et al.
patent: 5798741 (1998-08-01), Kajihara
patent: 6005542 (1999-12-01), Yoon
patent: 6052104 (2000-04-01), Lee
patent: 5-341732 (1993-12-01), None
patent: 6-161390 (1994-07-01), None

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