Liquid crystal cells – elements and systems – Particular structure – Having significant detail of cell structure only
Reexamination Certificate
2001-08-01
2004-09-28
Niebling, John F. (Department: 2812)
Liquid crystal cells, elements and systems
Particular structure
Having significant detail of cell structure only
Reexamination Certificate
active
06798477
ABSTRACT:
This application claims the benefit of Korean patent application No. 2000-44916, filed Aug. 2, 2000 in Korea, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device and a method of fabricating the same. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for improving a four-mask process, thereby resolving a problem of stitch lines.
2. Discussion of the Related Art
Generally, a liquid crystal display (LCD) device includes an upper substrate, a lower substrate, and an interposed liquid crystal therebetween. The upper and lower substrates respectively have electrodes opposing to each other. When an electric field is applied between the electrodes of the upper and lower substrates, molecules of the liquid crystal are aligned according to the electric field. By controlling the electric field, the liquid crystal display device provides various transmittances for rays of light to display images.
By now, an active matrix LCD (AM LCD) device is the most popular because of its high resolution and superiority in displaying moving video data. A typical AM LCD device has a plurality of switching elements and pixel electrodes, which are arranged in an array matrix on the lower substrate. Therefore, the lower substrate of the AM LCD device is alternatively referred as an array substrate.
On the upper substrate of the AM LCD device, a common electrode made of a transparent conductive material is usually formed. In case of a color LCD device, a color filter is further formed between the upper substrate and the common electrode of the upper substrate.
The above-mentioned lower substrate and the upper substrate are attached together with each other using a sealant therebetween. A liquid crystal is then interposed into a cell gap formed between the upper and lower substrates.
Because the pixel and common electrodes, as mentioned above, are respectively positioned on the lower and upper substrates, the electric field induced therebetween is perpendicular to the lower and upper substrates. The above-mentioned liquid crystal display device has high transmittance and aperture ratio. In addition, since the common electrode on the upper substrate serves as a ground, static electricity destroying the liquid crystal display device is eliminated.
At this point, there exist various intervals around the pixel electrode or other elements. If rays of light pass through the intervals, abnormal images may be displayed. To avoid a leakage of light, the upper substrate further includes a black matrix. The black matrix shields the intervals, thereby preventing rays of light from passing through the intervals.
Five or six masks were conventionally used in a masking step for fabricating the array substrate for an LCD device. Since the masking step includes a plurality of sub-steps including cleaning, depositing, baking, etching, and the like, if one masking step can be reduced, fabrication time and cost greatly decrease. Therefore, a research for decreasing the total number of masks has been actively performed such that four masks are now using in fabricating the LCD device.
Referring to
FIGS. 1 and 2
, an array substrate is fabricated by applying a conventional four-mask processing.
FIG. 1
is a plane view illustrating the array substrate while
FIG. 2
is a cross-sectional view taken along the line II—II of FIG.
1
.
As shown, a gate line
21
is disposed on the array substrate
10
, and a gate electrode
22
protrudes from the gate line
21
in the direction perpendicular to the gate line
21
. A gate insulating layer
30
is disposed to cover the gate line
21
including the gate electrode
22
. An undoped amorphous silicon layer
41
and a doped amorphous silicon layer
52
are sequentially are disposed on the gate insulating layer
30
. The undoped amorphous silicon layer
41
disposed over the gate line
22
serves as an active layer (hereinafter, the reference numeral
41
) while the doped amorphous silicon layer
52
disposed on the active layer
41
serves as an ohmic contact layer (hereinafter, the reference numeral
52
).
On the ohmic contact layer
52
, a data line
61
perpendicularly crossing the gate line
21
, a source electrode
62
and a drain electrode
63
are disposed thereon. The source electrode
62
protrudes from the data line
61
while the drain electrode
63
is spaced apart from the source electrode
62
with the gate electrode
22
centering on therebetween.
The gate electrode
22
, the source electrode
62
, the drain electrode
63
, and the active layer
41
collectively define a thin film transistor “T”, which serves as a switching element of the LCD device. Further, a passivation layer
71
is formed to cover all of the data line
61
, the source electrode
62
, and the drain electrode
63
. The passivation layer
71
has the same shape as the active layer
41
in the plane view of FIG.
1
. In a pixel region “P” defined by the crossing gate and data lines
21
and
61
, a pixel electrode
81
formed of a transparent conductive material is disposed thereon.
As previously mentioned, a black matrix formed on a color filter substrate is used for preventing rays of light from leaking through various intervals around the pixel electrode
81
.
FIG. 3
shows the black matrix
90
, which covers the above-mentioned electrical lines and electrodes except for the pixel electrode
81
.
With reference to
FIGS. 4A
to
4
C and
FIG. 2
, conventional process steps for fabricating the above-mentioned array substrate is explained hereinafter. These process steps have been suggested in U.S. patent application Ser. No. 09/885,527.
In
FIG. 4A
, a first metal layer is deposited on the array substrate
10
and patterned using a first mask to form the gate electrode
22
and the gate line (not shown).
In
FIG. 4B
, the gate insulating layer
30
, an amorphous silicon layer
40
, a doped amorphous silicon layer, and a second metal layer are sequentially deposited on the array substrate
10
. The second metal layer and the doped amorphous silicon layer are subsequently patterned using a second mask such that the data line
61
, the source electrode
62
, the drain electrode
63
, and the ohmic contact layer
52
are formed. A portion
52
a
(shown in
FIG. 6A
) of the doped amorphous silicon layer below the data line
61
is protected from etching processes, thereby remaining even after the etching processes. Sputtering is preferably used for depositing the second metal layer, and photolithography is preferably used for patterning in the above processes.
In
FIG. 4C
, silicon nitride or silicon oxide is deposited on the array substrate
10
and then patterned together with the amorphous silicon layer (shown in the reference numeral
40
of
FIG. 4B
) using a third mask. As a result, the passivation layer
71
and the active layer
41
are formed thereon. The passivation layer
71
covers the data line
61
, the source electrode
62
, and the drain electrode
63
. The side edge of the drain electrode
63
is however exposed out of the passivation layer
71
.
As shown in
FIG. 2
, a transparent conductive material is deposited on the array substrate
10
and patterned using a fourth mask such that the pixel electrode
81
is formed thereon. The pixel electrode
81
contacts the exposed side edge of the drain electrode
63
. Further, the pixel electrode
81
overlaps a portion of the previous gate line
21
a
that precedes the gate line
21
defining the pixel region “P”.
As explained above, because only four masks are used in fabricating the array substrate, a fabrication cost can be reduced.
An exposure apparatus is used for photolithography of the above-explained method. The exposure apparatus can expose only a specific area at one time. Therefore, if a substrate to be exposed is much larger than the specific area of the exposure apparatus, a step-and-repeat exposure process is applied
Jung Yu-Ho
Kim Hu-Sung
Kim Yong-Wan
Kwak Dong-Yeung
Lee Woo-Chae
LG.Philips LCD Co. , Ltd.
Morgan & Lewis & Bockius, LLP
Niebling John F.
Stevenson Andre′
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