Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Including integrally formed optical element
Reexamination Certificate
1998-07-02
2001-02-20
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Making device or circuit emissive of nonelectrical signal
Including integrally formed optical element
C438S149000, C349S139000, C349S143000, C349S149000
Reexamination Certificate
active
06190934
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an active matrix display panel (or active panel) used for a liquid crystal display device (or LCD) and a method of manufacturing the same. More specifically, the present invention relates to a method for manufacturing an active panel in which a structure of a gate pad and a source pad connected to a gate line and a source line, respectively, is arranged to protect against damage to the gate pad caused by a probe pin during an auto probe process done for testing quality of the active panel.
2. Description of Related Art
A CRT (Cathode Ray Tube) has recently been replaced by a thin flat panel display device because the thin flat panel display device is thinner and lighter than the CRT such that the thin flat panel display can be used in any space. Active research activities have focused on developing liquid crystal display devices because of the high resolution and fast response time suitable for display of motion pictures which are achieved by liquid crystal display devices. Furthermore, the active panel comprising an active switching element such as a thin film transistor (or TFT) is more frequently applied to the LCD.
The general structure of the active panel having a plurality of TFTs is shown in
FIG. 1. A
plurality of gate lines
13
extending in a horizontal direction are arranged in a column direction so as to be parallel to each other and a plurality of source lines
23
are arranged to extend vertically in the row direction parallel to each other. The gate lines
13
and source lines
23
are provided on a transparent insulating substrate
1
such as a non-alkalic glass. A gate pad
15
and a source pad
25
are located at each end of the gate lines
13
and source lines
23
. The TFT includes a gate electrode
11
, a gate insulating layer (not shown), a semiconductor layer
33
, a source electrode
21
and a drain electrode
31
. The gate electrode
11
of the TFT extends from the gate line
13
and the source electrode
21
is extends from the source line
23
. The drain electrode
31
is electrically connected to a pixel electrode
41
located at the area surrounded by each gate line
13
and each source line
23
.
FIGS. 2-4
are cross-sectional views along section lines II—II, III—III and IV—IV of
FIG. 1
, respectively, and illustrate a method of manufacturing a conventional active panel.
Aluminum or an aluminum alloy is deposited on a transparent insulating substrate
1
using a sputtering process in order to form an aluminum layer. A low resistance gate line
13
a
and a low resistance gate pad
15
a
(hereinafter referred to as a first gate pad
15
a
) are formed by patterning the aluminum layer using a photolithography process. The low resistance gate line
13
a
extends along a row direction of the pixel array A plurality of the low resistance gate lines
13
a
are arranged in a column direction of the pixel array The first gate pad
15
a
is formed at each low resistance gate line
13
a
, as shown in
FIGS. 2
a
and
3
a.
A gate electrode
11
, a gate line
13
and a second gate pad
15
are formed by depositing a metal layer including at least one of chromium, molybdenum, tantalum or antimony and also by patterning the metal layer. In contrast to the first gate pad
15
a
, the second gate pad is not formed of a low resistance metal but instead is formed of one of the highly reflective metals such as chromium, molybdenum, tantalum or antimony. The gate line
13
is arranged so as to cover the lower resistance gate line
13
a
. The gate electrode
11
extends from the gate line
13
and is arranged at one corner of the pixel array. The second gate pad
15
is arranged to cover the first gate pad
15
a
and to be electrically connected to the gate line
15
, as shown in
FIGS. 1
,
2
b
and
3
b.
A gate insulating layer
17
is formed by depositing a silicon nitride (SiN
x
) or silicon dioxide (SiO
2
) on the substrate using a chemical vapor deposition (CVD) process, as shown in
FIGS. 2
c
,
3
c
and
4
a.
As shown in
FIGS. 1 and 2
d
, a semiconductor layer
33
and a doped semiconductor layer
35
are formed by depositing an amorphous silicon and n+ amorphous silicon layer sequentially on the gate insulating layer
17
using a CVD and then patterning these layers using a photo-lithography technique The semiconductor layer
33
defines a channel layer. The doped semiconductor layer
35
helps the source electrode
21
and the drain electrode
31
, which are formed later, to be in ohmic contact with the semiconductor layer
33
.
A source electrode
21
, a drain electrode
31
, a source line
23
and a source pad
25
are formed by depositing chromium or a chromium alloy to form a chromium layer using a sputtering method and then patterning the chromium layer using a photolithography technique. Then, the exposed doped semiconductor layer
35
located between the source electrode
21
and the drain electrode
31
is removed by using a dry etching method while using the source electrode
21
and the drain electrode
31
as a mask. The source electrode
21
is overlapped with one side of the gate electrode
11
located between the doped semiconductor layer
35
. The drain electrode
31
facing the source electrode
21
is overlapped with the other side of the gate electrode
11
between the doped semiconductor layer
35
. The source line
23
extends along a column direction of the pixel array and a plurality of source lines
23
are arranged at intervals along the row direction. The source pad
25
is formed at the end of the source line
23
, as shown in
FIGS. 1
,
2
e
and
4
b.
A passivation layer
37
is formed by depositing a silicon nitride material on the resulting substrate using a CVD process A drain contact hole
71
, a gate contact hole
59
and a source contact hole
69
are formed by patterning the passivation layer
37
using a photolithography process. The drain contact hole exposes a portion of the drain electrode
31
. The gate contact hole
59
and the source contact hole
69
expose a portion of the second gate pad
15
and the source pad
25
, respectively, as shown in
FIGS. 1
,
2
f
,
3
d
and
4
c.
Finally, a pixel electrode
41
, a gate pad terminal
57
and a source pad terminal
67
are formed by depositing and patterning a transparent conductive material such as an indium-tin-oxide (or ITO) on the passivation layer
37
. The pixel electrode
41
is electrically connected to the drain electrode
31
through the drain contact hole
71
. The gate pad terminal
57
and the source pad terminal
67
are connected to the second gate pad
15
and the source pad
25
through the gate contact hole
59
and the source contact hole
69
, respectively, as shown in
FIGS. 1
,
2
g
,
3
e
and
4
d.
The structure of the conventional active panel of an LCD manufactured according to the method described above includes a gate electrode
11
made of at least one of chromium, molybdenum, tantalum or antimony and is disposed on a transparent insulating substrate
1
. A gate insulating layer
17
comprising silicon nitride or silicon oxide covers the surface of the substrate
1
including the gate electrode
11
. A semiconductor layer
33
is formed on the gate insulating layer
17
so as to cover the gate electrode
11
. Two doped semiconductor layers
35
including an impurity doped semiconductor material made of phosphorous, such as an n+ amorphous silicon, are formed on the two sides of the semiconductor layer
33
. A source electrode
21
and a drain electrode
31
including chromium or molybdenum are formed on the two doped semiconductor layers
35
. A passivation layer
37
is formed on the substrate
1
including the source electrode
21
and the drain electrode
31
. The drain electrode
31
is electrically connected to the pixel electrode
41
including an ITO through the drain contact hole
71
.
The first gate pad
15
a
made of low resistance material such as aluminum is formed on the substrate
1
. A second gate pad
15
including at least
Huh Jung Chul
Kang Sung Gu
Kim Jeom Jae
Davis Jamie L.
Jr. Carl Whitehead
LG.Philips LCD Co. , Ltd.
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