Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2001-06-15
2002-02-05
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S637000, C438S656000, C438S669000
Reexamination Certificate
active
06344377
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a pad terminal for inputting or outputting electrical signals. More particularly, the present invention relates to a structure of the pad terminal in an electrical circuit board or a liquid crystal display device, and a method of manufacturing of the pad terminal.
2. Discussion of the Related Art
Generally, most electrical circuit boards have pad terminals for inputting or outputting electrical signals. These pad terminals are usually made simultaneously with the rest of the circuit board. Also, an LCD display comprising thin film transistors (TFT's) or other electrical elements has pad terminals similar to ordinary electric circuit boards. The LCD comprises a color filter panel for representing the color of a picture, and an active panel driving a pixel array by applying a data signal corresponding to the picture. These two panels are joined to each other with a narrow gap in between, and a liquid crystal material is injected into the gap. When driving signals are applied to the pad terminals of the active panel, the TFT's of the active panel drive the liquid crystal, thus displaying an image.
The color filter panel comprises a red color filter, a green color filter, and a blue color filter which are arrayed in sequence. A black matrix is located between the color filters in a mesh pattern. A common electrode is formed on the black matrix. The active panel comprises pixel electrodes at the pixels arrayed on the transparent substrate in a matrix pattern. A scan line is formed along the horizontal direction of the pixel array, and a data line is formed along the vertical direction of the pixel array. At one corner of the pixel, a thin film transistor is formed for driving the pixel electrode. The gate electrode is connected to the scan line (sometimes referred to as a ‘gate line’), and the source electrode is connected to the data line (sometimes referred to as a ‘source line’). A pad terminal is formed at the end portion of each line.
The scan signal and the data signal are applied to the active panel through the pad terminals. The scan signal is used for selecting the horizontal scan line and has a frequency from 30 Hz to 60 Hz. The data signal normally represents an image. By selecting one scan line using the scan signal, the data signal of the scan line can be displayed an the LCD panel.
The signal applied to the pad terminal is an electrical signal. If there are particles or contaminants between the pad terminal and the output terminal of the outer device, or if the electrical contact between them is poor, then the quality of the image on the LCD screen may degrade. Therefore, the process of forming a pad terminal is very important for maintaining the quality of the image. The conventional method for manufacturing the pad terminal and the structure of the LCD will now be described.
FIG. 1
shows a plan view of the conventional structure of an LCD.
FIGS. 2
a
-
2
f
are cross-sectional views showing the conventional process for manufacturing the TFT, the gate line, and the gate pad of an LCD along the line II—II.
A metal layer having low resistance such as aluminum or an aluminum alloy is deposited on a transparent substrate
11
. A gate electrode
13
, a gate line
15
, a gate pad
17
, and a source pad
37
are formed by patterning the metal layer using a photolithographic method, as shown in
FIG. 2
a.
The gate electrode
13
is formed at one corner of the pixel. The gate line
15
connects the gate electrodes
13
arrayed in a row direction. The gate pad
17
is formed later at an end portion of the gate line
15
. The source pad
37
is formed at an end portion of a source line
35
.
A gate insulation layer
19
is formed by depositing an insulation material such as silicon nitride or silicon oxide on the substrate having the gate electrode
13
, the gate line
15
, and the gate pad
17
. An intrinsic semiconductor material and a doped semiconductor material are sequentially deposited on the gate insulation layer
19
. By patterning them, a semiconductor layer
21
and a doped semiconductor layer
23
are formed, as shown in
FIG. 2
b.
A first gate pad contact hole
61
and a first source pad contact hole
71
are formed by patterning the gate insulation layer
19
, as shown in
FIG. 2
c.
The first gate pad contact hole
61
exposes the gate pad
17
by etching the gate insulation layer
19
covering the gate pad
17
. The first source pad contact hole
71
exposes the source pad
37
by etching the gate insulation layer
19
covering the source pad
37
.
A metal such as chromium or a chromium alloy is deposited on the substrate having the doped semiconductor layer
23
. A source electrode
33
, a drain electrode
43
, a source pad intermediate electrode
77
, and a gate pad intermediate electrode
67
are formed by patterning the metal layer, as shown in
FIG. 2
d.
The source electrode
33
contacts one side of the semiconductor layer
21
and the doped semiconductor layer
23
, which acts as a source region. The source line
35
connects to the source electrodes
33
arrayed in a column direction. The drain electrode
43
is on the other side of the doped semiconductor layer
23
from the source electrode
33
, and connects to the other side of the semiconductor layer
21
and the doped semiconductor layer
23
, which acts as a drain region. The source pad intermediate electrode
77
is formed at the end of the source line
35
and connects to the source pad
37
through the first source pad contact hole
71
. The gate pad intermediate electrode
67
connects to the gate pad
17
through the first gate pad contact hole
61
.
A protection layer
39
is formed by depositing an insulation material such as silicon oxide or silicon nitride on the substrate having the source electrode
33
. A drain contact hole
81
, a second gate pad contact hole
87
, and a second source pad contact hole
97
are formed by patterning the protection layer
39
, as shown in
FIG. 2
e.
The drain contact hole
81
exposes the drain electrode
43
by removing a portion of the protection layer
39
covering the drain electrode
43
. The second gate pad contact hole
87
exposes the gate pad intermediate electrode
67
by removing a portion of the protection layer
39
covering the gate intermediate electrode
67
. The source pad contact hole exposes the source intermediate electrode
77
by removing a portion of the protection layer
39
covering the source intermediate electrode
77
.
A pixel electrode
53
, a gate pad terminal
65
, and a source pad terminal
75
are formed by depositing and patterning indium tin oxide (ITO) on the protection layer
39
, as shown in
FIG. 2
f.
The pixel electrode
53
connects to the drain electrode
43
through the drain contact hole
81
. The gate pad terminal
65
connects to the gate pad intermediate terminal
67
through the second gate pad contact hole
87
. The source pad terminal
75
connects to the source pad intermediate electrode
77
through the second source pad contact hole
97
.
According to the conventional method, the gate pad
17
and the source pad
37
comprise aluminum, the gate and source pad intermediate electrodes
67
and
77
comprise chromium, and the gate source pad terminals
65
and
75
comprise ITO. Generally, when ITO is deposited by a sputtering method on the intermediate electrodes
67
and
77
, it is sputtered in an oxygen atmosphere. At that time, chromium oxide can form on the surface of the intermediate electrodes
67
and
77
. Also, the gate insulation layer or the protection layer comprising the silicon oxide or silicon nitride are formed on the pads or on the intermediate electrodes and patterned to form contact holes. When silicon oxide or silicon nitride is deposited on the surface of the metal layer, a thin metal oxide layer or a thin metal nitride layer can form, resulting in a contact resistance between chromium and ITO that is higher than desired.
SUMMARY OF THE INVENTION
Accordi
Ahn Byung Chul
Choi Jae Beom
Kim Chang Dong
Seo Hyung Sik
Soh Hoe Sup
LG. Philips LCD Co. Ltd.
Long Aldridge & Norman LLP
Quach T. N.
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