Linked component extraction circuit for image processor

Details Linked component extraction circuit for image processor Linked component extraction circuit for image processor

1985-03-27

1986-11-18

Boudreau, Leo H.

Image analysis

Histogram processing

For setting a threshold

382 26, 382 48, G06K 900

Patent

active

046240136

ABSTRACT:
A linked component extraction circuit has a FIFO memory for sequentially storing information pairs each consisting of two label values which are generated from a linked component detector and which have a linking relationship therebetween, and for reading out a currently oldest information pair when the FIFO memory is subjected to read access. A read/write unit reads out storage data (i.e., the label value) from a memory area of the table memory at an address accessed by the first label value of the information pair or the readout output data and writes the second label value of the information pair read out from the FIFO memory at the same address. The storage data read out from the table memory at the address accessed by the first label value is compared with the first label value by a comparator to generate a coincidence or noncoincidence signal. When noncoincidence is detected by the comparator, the storage data is used as the address for read/write operation of the read/write unit until the next coincidence signal is generated by the comparator. When coincidence is detected by the comparator, the next information pair is read out from the FIFO memory, and the above operation is repeated.

REFERENCES:
patent: 4069411 (1978-01-01), Morton
patent: 4183013 (1980-01-01), Agraawala et al.
patent: 4189711 (1980-02-01), Frank

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