Process for making CMOS device with both P+ and N+ gates includi

Details Process for making CMOS device with both P+ and N+ gates includi Process for making CMOS device with both P+ and N+ gates includi

1989-10-05

1991-04-23

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437200, 437190, 437192, 437 52, 148DIG147, H01L 21336

Patent

active

050100327

ABSTRACT:
A process for making CMOS device wherein the N-channel devices have n+ gates, and the P-channel devices have p+ gates. A TiN local interconnect system is used to connect the two types of gates, as well as providing connections to moat. A titanium nitride layer may be formed by depositing titanium metal everywhere, and then heating the integrated circuit structure in a nitrogen atmosphere. This process may also be used with other refractory metal nitride interconnect layers. In addition to titanium based thin film compositions, other metals can be substituted and used for direct-react silicidation and simultaneous formation of a conductive nitride to form local interconnects, including molybdenum, tungsten, vanadium, cobalt, and others.

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