Link power saving state

Details Link power saving state Link power saving state

2007-12-25

2007-12-25

Perveen, Rehana (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S300000, C713S320000

Reexamination Certificate

active

10850733

ABSTRACT:
Disclosed are embodiments of a method, apparatus and system for a low power state for a point-to-point link. During the low power state, the signal on both conductors of a differential transmit pair are driven to electrical idle. Analog activity detectors are enabled during the low power state and are disabled during normal power state. Exit from the low power state does not require a physical layer re-initialization sequence. Other embodiments are also described and claimed.

REFERENCES:
patent: 5706110 (1998-01-01), Nykanen
patent: 6463542 (2002-10-01), Yu et al.
patent: 6526469 (2003-02-01), Drehmel et al.
patent: 6593801 (2003-07-01), Hattori
patent: 7028199 (2006-04-01), Ayyavu et al.
patent: 7197654 (2007-03-01), Olsen
patent: 2003/0198296 (2003-10-01), Bonelli et al.
patent: 2004/0103333 (2004-05-01), Martwick et al.
patent: 2005/0215274 (2005-09-01), Matson et al.
PCI Express Base Specification, Revision 1.0, Jul. 22, 2002, pp. 1-8 and 165-189.
Ajay V. Bhatt, Intel Corporation, “Creating a Third Generation I/O Interconnect”, White Paper, 2002, 8 pages.
Steve Krig, Intel Corporation, “Intitiatives and Technologies”, White Paper, 2003, 8 pages.

Affiliated with

Also associated with

Rating

Link power saving state does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Link power saving state, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Link power saving state will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3893417