Linearized digital phase-locked loop method for maintaining...

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Reexamination Certificate

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C375S376000

Reexamination Certificate

active

07826581

ABSTRACT:
An apparatus and method are disclosed synchronization of a clock signal to a data signal. The apparatus includes a phase lock and tracking logic circuit configured to detect a plurality of values. Each of the plurality of values indicates a position of a data edge of the data signal. The phase lock and tracking logic circuit adds the plurality of values to generate a result and to adjust the clock signal if the result is greater than a predetermined value, or threshold. The phase lock and tracking logic circuit may be configured to maintain the clock signal linearity approximately between the end of a first data packet and the beginning of a second data packet.

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