Electronic digital logic circuitry – Multifunctional or programmable – Sequential or with flip-flop
Reexamination Certificate
1999-05-13
2001-01-30
Nelms, David (Department: 2818)
Electronic digital logic circuitry
Multifunctional or programmable
Sequential or with flip-flop
C326S040000, C326S041000
Reexamination Certificate
active
06181164
ABSTRACT:
REFERENCED PATENT APPLICATIONS
The present invention is related to the patent application entitled, “LOOKUP TABLES WHICH DOUBLE AS SHIFT REGISTERS,” by Bauer, having serial number 08/754,421 and a filing date of Nov. 22, 1996, and assigned to the assignee of the present invention, which is herein incorporated by reference.
FIELD OF THE INVENTION
The present invention generally relates to linear feedback shift registers, and more particularly to a programmable gate array implementation of a linear feedback shift register.
BACKGROUND
Field programmable gate arrays (FPGAs), first introduced by XILINX in 1985, are becoming increasingly popular devices for use in electronics systems. For example, communications systems employ FPGAs in large measure for their re-programmability. In general, the use of FPGAs continues to grow at a rapid rate because they permit relatively short design cycles, reduce costs through logic consolidation, and offer flexibility in their re-programmability. The capabilities of and specifications for XILINX FPGAs are set forth in “The Programmable Logic Data Book,” published in 1998 by XILINX, Inc., the contents of which is incorporated herein by reference.
Linear feedback shift registers (LFSRs) are commonly used in applications for generating pseudo-random noise sequences. The pseudo-random noise sequences are commonly referred to as “PN codes” or “PN sequences.” Such noise sequences have a diverse range of uses, several of which are found in spread spectrum communications systems. The growing popularity of wireless communications systems has lead to the adoption of spread spectrum technology in an attempt to maximize utilization of the available radio signal bandwidth.
LFSR's are at the heart of every spread spectrum system as they are used to uniquely code each subscriber signal and spread the transmission signal across a wide range of frequencies. An LFSR generally comprises a shift register of one bit memory elements and an XOR feedback path. An LFSR can be achieved in both FPGA and ASIC technologies. However, it is always desirable to achieve a given functionality using the minimum number of resources since silicon resources of both ASICs and FPGAs are finite.
An example spread spectrum system, the Universal Mobile Telecommunication System (UMTS), requires a number of LFSRs that must be periodically set to a predefined state at a known time interval. The UTMS specification is controlled and maintained by the European Telecommunications Standards Institute (ETSI). This specification implies an LFSR structure that requires parallel access to all stages in the shift register such that the shift register's contents can be modified in one cycle of the LFSR clock rate. Implementing parallel access to the shift register stages requires additional logic resources, which is contrary to the objective of using as few resources as possible.
An apparatus that satisfies the aforementioned requirements, as well as other related requirements, is therefore desirable.
SUMMARY OF THE INVENTION
In various embodiments, the invention comprises a linear feedback shift register in a programmable logic device. A first lookup table is configured as a shift register having n selectable taps and a shift-input. A second lookup table is configured as a parity generator and has inputs coupled to the n selectable taps and an output coupled to the shift-input of the shift register.
In another embodiment, an n-stage linear feedback shift register with m taps is provided. The linear feedback shift register comprises m n-stage shift registers, m n:1 multiplexers, and a parity generator. The m n-stage shift registers each have n outputs and a respective data input. The m n:1 multiplexers have data inputs respectively coupled to the outputs of the n-stage shift registers, and each of the m n:1 multiplexers has log
2
n selection inputs, wherein the shift registers and multiplexers are implemented with respective look-up tables in the programmable gate array. The parity generator has inputs coupled to outputs of the multiplexers and an output coupled to the data inputs of the shift registers.
In another embodiment, an n-stage linear feedback shift register with m taps in a programmable gate array is provided. The linear feedback shift register comprises an n-stage shift register, an n:1 multiplexer, and a lookup table configured as an XOR function generator. The n-stage shift register has n outputs, a data input, and is operable at a first frequency at which data are shifted responsive to a first clock frequency. The n:1 multiplexer has data inputs respectively coupled to the outputs of the shift register, log
2
n selection inputs, and is operable at a second frequency at which the inputs are selectable responsive to a second clock frequency that is m× the first clock frequency. The shift register and multiplexer are implemented with a look-up table in the programmable gate array. The lookup table configured as an XOR function generator has a first input coupled to the output of the multiplexer, a second input, and an output coupled to the data input of the shift register. A flip-flop has a data input coupled to the output of the XOR function generator, an output coupled to the second input of the XOR function generator, and is clocked at the second clock frequency.
In other embodiments, Gold code generators are provided. A Gold code generator includes an additional XOR function generator that receives as input, output from the last stages of two linear feedback shift registers. The output of the XOR function generator provides the Gold code.
The above summary of the present invention is not intended to describe each disclosed embodiment of the present invention. The figures and detailed description that follow provide additional example embodiments and aspects of the present invention.
REFERENCES:
patent: 5383204 (1995-01-01), Gibbs et al.
patent: 5729559 (1998-03-01), Bright et al.
patent: 5889413 (1999-03-01), Bauer
“The Programmable Logic Data Book” published in 1998 by Xilinx, Inc., available from Xilinx Inc., 2100 Logic Drive, San Jose, California 95124.
Xilinx, Virtex TM Field Programmable Gate Array, Nov. 9, 1998 (Version 1.1—Advance), pp. 1-43.
Lam David
Maunu LeRoy D.
Nelms David
Xilinx , Inc.
Young Edel M.
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