Linear delay element providing linear delay steps

Details Linear delay element providing linear delay steps Linear delay element providing linear delay steps

2000-09-14

2003-04-08

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C327S278000

Reexamination Certificate

active

06546530

ABSTRACT:

TECHNICAL FIELD
The present invention relates to the field of signal delay devices for integrated circuits, and more particularly to digital delay elements that generate linear steps.
BACKGROUND INFORMATION
Signal delay devices have a function to delay a signal in accordance with an arbitrarily set control signal. For example, integrated circuits generally require delay circuits to compensate for differences in operating speeds of elements so that data does not arrive at a location before the desired time. One method to compensate for differences in operating speeds is to implement a digital delay locked loop (“DLL”). Typically, DLL's have been limited to course variable delays where the incremental delay is one or two logic gates providing one or two block delay units, respectively.
For synchronized interconnects in a digital system, a clocking dictates when a driver circuit places new data on the interconnection line, and when the receiver samples that data at the other end of the line. The main problem with the clocking method is the timing uncertainty problem. There are two types of timing uncertainties. One type of timing uncertainty is the fixed timing uncertainty or skew which is caused by the delay variation between the interconnects. The other type of timing uncertainty is the time-varying uncertainty or jitter which is caused by signal amplitude, power supply noise and temperature variation. The timing uncertainty problem may be solved by having the transmitted data sampled at the time instant during which the data is most unlikely to change. That occurs when the sampling event is at the center of the eye, i.e., middle, of the clock pulse.
Unfortunately, these variable delay devices, e.g., DLL's, have variable incremental delays. By having variable incremental delays, data may not arrive at the eye, i.e., middle, of the clock pulse. When the data does not arrive at the eye of the clock pulse, the data may become skewed and hence decrease the overall performance of the integrated circuit.
It would therefore be desirable to develop a delay device that generates linear delay steps within a certain range to optimize placement of data. It would further be desirable to develop a delay device that has the capability of being tested and programmed while generating linear delay steps. It would further be desirable to develop a linear delay device with reduced power.
SUMMARY
The problems outlined above may at least in part be solved in some embodiments by providing a linear delay element comprising a fine delay element and at least one course delay element where the linear delay element is configured to provide linear delay steps as well as configured to provide testability and programmability. In another embodiment of the present invention, the linear delay element operates with reduced power.
In one embodiment, circuitry in an integrated circuit for linearly delaying a signal comprises a plurality of control signals. The circuitry further comprises a fine delay element coupled to at least one of the plurality of control signals where the fine delay element comprises logic circuitry configured to provide fine adjustments to the delay of the signal. The circuitry further comprises at least one course delay element coupled to the fine delay element where the at least one course delay element is coupled to at least one of the plurality of control signals. Furthermore, the at least one course delay element comprises logic circuitry configured to provide course adjustments to the delay of the signal. The circuitry for linearly delaying a signal is configured to provide both testability and programmability. The circuitry for linearly delay a signal is configured to provide linear delay steps.
In another embodiment of the present invention, a test signal is coupled to the fine delay element and to the at least one course delay element. The test signal is used to detect faults at the fine delay element and at the at least one course delay element. During the functional mode of this embodiment, power is reduced by disconnecting the test path during the functional mode.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.


REFERENCES:
patent: 5243227 (1993-09-01), Gutierrez et al.
patent: 5376849 (1994-12-01), Dickol et al.
patent: 6330197 (2001-12-01), Currin et al.

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