Linear dead-band-free digital phase detection

Details Linear dead-band-free digital phase detection Linear dead-band-free digital phase detection

2006-01-10

2006-01-10

Chin, Stephen (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S371000, C375S373000

Reexamination Certificate

active

06985551

ABSTRACT:
A phase-locked loop includes a phase detector, a loop filter, a voltage controlled oscillator and a frequency divider arranged such that the phase detector generates a phase detector output signal as a function of a phase difference between the reference clock signal and the feedback signal; the loop filter generates a frequency control signal from the phase detector output signal; the voltage controlled oscillator generates a phase-locked loop output signal that has a frequency that is controlled by the frequency control signal; and the frequency divider generates the feedback signal from the phase-locked loop output signal. The phase-locked loop further includes one or more circuit elements that maintain an operating point of the phase detector such that, for a predetermined range of both positive and negative phase differences between the reference clock signal and the feedback signal, the output signal is generated as a substantially linear function of the phase difference between the reference clock signal and the feedback signal.

REFERENCES:
patent: 4818950 (1989-04-01), Ranger
patent: 5103191 (1992-04-01), Werker
patent: 5631582 (1997-05-01), Fujikawa
patent: 6002273 (1999-12-01), Humphreys
patent: 6049233 (2000-04-01), Shurboff
patent: 0 458 269 (1991-11-01), None
D. P. Turner: “Phase Locked Loop Phase Adjustment” IBM Technical Disclosure Bulletin, US, IBM Corp. New York, vol. 15, No. 7, Dec. 1972, pp. 2080-2081.

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