Electronic digital logic circuitry – Interface – Logic level shifting
Reexamination Certificate
2001-09-12
2004-04-27
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Interface
Logic level shifting
C326S027000, C326S083000
Reexamination Certificate
active
06727729
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to electronic circuitry. More particularly, the present invention relates to buffers.
2. Background Art
Buffer circuits typically are used to drive a low impedance while providing a high input impedance. For example, buffer circuits may be used at the interface of continuous-time and discrete-time circuits such as switched-capacitor sampling circuits to avoid the effects caused by sampling of the preceding continuous-time signal. Accordingly, buffer circuits are commonly used at the input of switched-capacitor based analog-to-digital converters (ADCs) such as sigma-delta ADCs, pipeline ADCs, algorithmic ADCs, etc.
A source-follower transistor is conventionally used as a buffer. In their simplest forms, source-follower transistor based buffers do not often meet the high linearity characteristics desired for many buffer circuit applications. In addition, charge glitches caused by a sampling circuit that follows a buffer circuit are typically coupled to the buffer circuit's input terminal through a parasitic capacitance “C
gs
” of the source-follower transistor. This coupling can degrade the linearity of preceding continuous-time signals at the buffer circuit input. Accordingly, there is a need for a buffer circuit having high linearity.
Furthermore, buffer circuits, such as ones based on source-follower transistors, often generate an output signal having a level that is offset from the level of the corresponding buffer circuit input signal. It is often desirable to control the level of buffer output signals.
In addition, the level of a buffer circuit input signal may affect buffer circuit performance. Therefore, it is also often desirable to control the level of buffer input signals.
BRIEF SUMMARY OF THE INVENTION
The present invention provides buffer circuits that generate output signals from input signals with high linearity. In addition, the present invention provides buffer circuits that are capable of setting buffer input and output signal levels.
In one aspect of the present invention, a buffer includes a source-follower transistor adapted to generate an output signal from an input signal. A replica transistor is adapted to generate a replica signal from the input signal. A level-shifted replica signal generated by a level shifting circuit and provided at a terminal of the source-follower transistor. This level-shifted replica signal has a value so that the source-follower transistor is in saturation.
In a further aspect of the present invention, an interface circuit produces an output signal having an output signal level from an input signal and a reference signal. The input and output signals may be differential or single-ended. The output signal has an output direct current (dc) voltage level that is substantially equal to a dc voltage level of the reference signal. The interface circuit includes a level translation module that generates an input level control signal from the reference signal. A level adjustment module produces an adjusted buffer input signal from the input signal. The adjusted buffer input signal has a dc voltage level that is substantially equal to a dc voltage level of the input level control signal. A buffer generates the output signal from the adjusted buffer input signal.
The level translation module may include a replica buffer that generates a replica buffer output signal from the reference signal. In addition, the level translation module may include a difference amplifier, such as an operational amplifier (op-amp). The difference amplifier has a positive input terminal that receives the reference signal, a negative input terminal that receives the replica buffer output signal, and an output terminal that generates the input level control signal. The buffer and the replica buffer may both operate with substantially equal offsets.
In yet a further aspect of the present invention, a circuit includes a buffer, a sampling circuit having a switch, and a damping circuit coupled to the buffer and the sampling circuit. The damping circuit reduces charge glitches when the switch closes. The damping circuit may include a low pass filter, such as an RC low pass filter.
REFERENCES:
patent: 4168471 (1979-09-01), Sampei
patent: 5365199 (1994-11-01), Brooks
patent: 5666070 (1997-09-01), Merritt et al.
patent: 5786711 (1998-07-01), Choi
patent: 6043690 (2000-03-01), Krymski et al.
patent: 196 35 024 (1997-10-01), None
Patent Abstracts of Japan, vol. 010, No. 150, May 31, 1986, & JP 61 010305 A, Jan. 17, 1986, Abstract.
Brooks Todd L.
Tammineedi Anilkumar V.
Broadcom Corporation
Chang Daniel
Sterne Kessler Goldstein & Fox P.L.L.C.
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