Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-09-12
2006-09-12
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
07107554
ABSTRACT:
A machine-readable medium has a set of machine-readable instructions for causing a computer to perform a method. The method includes checking a layout having a layout line width for at least one line versus a schematic having a schematic line width for the at least one line. Extracting a line width property from the schematic and transferring the line width property to the layout are included in the method, as is checking a design for the at least one line versus the schematic.
REFERENCES:
patent: 5706295 (1998-01-01), Suzuki
patent: 5793643 (1998-08-01), Cai
patent: 5963729 (1999-10-01), Aji et al.
patent: 6038020 (2000-03-01), Tsukuda
patent: 6038383 (2000-03-01), Young et al.
patent: 6078737 (2000-06-01), Suzuki
patent: 6115546 (2000-09-01), Chevallier et al.
patent: 6295627 (2001-09-01), Gowni et al.
patent: 6425113 (2002-07-01), Anderson et al.
patent: 6446239 (2002-09-01), Markosian et al.
patent: 6470477 (2002-10-01), Scott
patent: 6516451 (2003-02-01), Patin
patent: 6546540 (2003-04-01), Igarashi et al.
Ababei Adriana
Chevallier Christophe
Bowers Brandon
Leffert Jay & Polglaze P.A.
Micro)n Technology, Inc.
Siek Vuthe
LandOfFree
Line width check in layout database does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Line width check in layout database, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Line width check in layout database will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3581184