Line self protecting multiple output power IC architecture

Details Line self protecting multiple output power IC architecture Line self protecting multiple output power IC architecture

2002-06-11

2004-08-31

Le, Dung A. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S502000, C257S549000

Reexamination Certificate

active

06784493

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to semiconductor devices, and more particularly, to semiconductor transistors including an LDMOS (lateral double-diffused metal oxide semiconductor) device.
BACKGROUND OF THE INVENTION
Battery-operated electronic systems such as notebook personal computers, personal digital assistants, and wireless communication devices often use power MOS (metal oxide semiconductor) devices as low on-resistance electronic switches for distributing battery power. For battery-operated application, low on-resistance can be particularly important to ensure as little power consumption to the battery as possible. This ensures long battery life.
DMOS devices are “double diffused” MOS devices. A DMOS device is characterized by a source region and a back gate region, which are diffused at the same time. The back gate region is sometimes referred to as a Dwell (double diffused well) region. The channel is formed by the difference in the two diffusions, rather than by separate implantation. DMOS devices have the advantage of decreasing the length of the channels, thus providing low-power dissipation and high-speed capability.
DMOS devices may have either lateral or vertical configurations. A DMOS device having a lateral configuration (referred to herein as an LDMOS), has its source and drain at the surface of the semiconductor wafer. Thus, the current is lateral. Desired characteristics of an LDMOS are a high breakdown voltage, BV, and a low specific on-resistance.
A conventional LDMOS configuration is shown at
10
in
FIG. 1
, with a source region shown at
11
, a drain region at
12
, a gate region at
13
, and a backgate region at
15
. Since the drain region
12
is integral to the NBL
14
, then it cannot be isolated in its own tank from the parasitic collection guardring consisting of NBL
14
and DEEP N+ well
16
. Therefore, when in use as a low side device driving an inductive load, as shown schematically in
FIG. 2
, then when device
10
is switched off or to a condition when the drain
12
of the device
10
consequently becomes negative, the integral parasitic diode D
2
from P-epi
18
/substrate
20
to Deep N+
16
, and the parasitic diode D
1
from the p-type backgate
24
to N-region
22
both conduct. As a consequence of this conduction, the P backgate
24
, P-epi
18
and substrate
20
build up a large amount of minority charge, in this case, electrons. When switched back on, or changed to a blocking state, the electrons either have to be recombined or collected by the drift field set up with an N type region that is positively biased. In the case of
FIG. 1
, the electrons in the P region
24
will have to recombine and will thus create a long recovery time. In the regions
18
and
20
the electrons will get collected by some other N region.
This method of collection can create a very large problem of classical latch-up if collection efficiency is low. Additionally, the extra collection guardring
14
and
16
uses a lot of silicon area and it is desired to eliminate this area usage.
An optimized tank—isolated drain device that overcomes these problems is needed in an advanced CMOS process capable of very high current operating conditions and switching through required breakdown. The improved device should reduce the minority carrier lifetime to improve switching speed. The on resistance performance of this device needs to be extremely competitive to enable the highest current possible at very low drive voltage in the smallest form factor package.
SUMMARY OF THE INVENTION
The present invention achieves technical advantages as a power integrated circuit architecture whereby a high side transistor is interposed between a control circuit and a low side transistor to reduce the effects of the low side transistor on the operation of the control circuit. Preferably, the low side transistor is designed to have a reduced minority carrier lifetime and an improved minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a collection ring tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit.
Advantageously, the low side transistor and high side transistor are separated from one another by a deep n-type region, and by a P-epi tank. The low side transistor is comprised of multiple transistor arrays partitioned by at least one deep n-type region, which deep n-type region forms a guardring about the respective transistor array. The guardring isolates minority carriers in one transistor array from another transistor array, and facilitates the collection of the minority carriers therethrough. The guardring of the low side transistor is preferably grounded, whereby the guardring of the high side transistor is preferably tied to a positive potential. Advantageously, the high side transistor being interposed between the control circuit and the low side transistor further collects any minority carriers that are not collected by the low side transistor.


REFERENCES:
patent: 5939755 (1999-08-01), Takeuchi et al.
patent: 6160304 (2000-12-01), Ludikhuize
patent: 6225673 (2001-05-01), Pendharkar et al.

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