Line receiver circuit having termination impedances with transmi

Details Line receiver circuit having termination impedances with transmi Line receiver circuit having termination impedances with transmi

1998-11-06

2000-03-14

Tokar, Michael

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

326 83, 326113, H03K 1716, H03K 19003

Patent

active

060377984

ABSTRACT:
A line receiver circuit featuring an integrated input amplifier circuit having a non-inverting input terminal and an inverting input terminal for connection with a transmission line. The circuit features a line termination impedance means for terminating the characteristic impedance of the transmission line with the input amplifier circuit and the line termination impedance means integrated on a common semiconductor substrate. The line termination impedance means features a series connection of a plurality of impedances where at least one of the impedances has a transmission gate connected in parallel. The transmission gates feature a parallel connection of an N-channel MOSFET and a P-channel MOSFET where the gate of the N-channel MOSFET is connected to receive a transmission control signal, and the gate of the P-channel MOSFET is connected to receive the inverted transmission control signal.

REFERENCES:
patent: 4991140 (1991-02-01), Wang et al.
patent: 5371420 (1994-12-01), Nakao
patent: 5396028 (1995-03-01), Tomassetti
patent: 5528168 (1996-06-01), Kleveland
patent: 5530377 (1996-06-01), Walls
patent: 5559448 (1996-09-01), Koenig
patent: 5570037 (1996-10-01), Llorens
"On-chip Programmable Termination Scheme" IBM Technical Disclosure Bulletin, vol. 38, No. 2, Feb. 1995, New York US, pp. 483-485.

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