Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2006-09-19
2006-09-19
Paladini, Albert W. (Department: 2125)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
Reexamination Certificate
active
07110933
ABSTRACT:
A method of a modeling metallization parasitics with the use of a simulation program. In one embodiment, a method of simulating interconnect lines in an electronic design automation simulation is disclosed. The method comprises partitioning the interconnect lines into groups of interconnect lines. Each group of interconnect lines does not have interactions with any of the other groups of interconnect lines. Moreover, at least one of the groups of interconnect lines contains at least three interconnect lines. The interconnect lines in each group are modeled. The modeling includes at least one of modeling mutual inductances and modeling of mutual capacitances.
REFERENCES:
patent: 4703482 (1987-10-01), Auger et al.
patent: 5081602 (1992-01-01), Glover
patent: 5949991 (1999-09-01), LeBlanc
patent: 6167364 (2000-12-01), Stellenberg et al.
patent: 6353801 (2002-03-01), Sercu et al.
patent: 6915500 (2005-07-01), Teig et al.
Croft Gregg D.
Czagas Joseph A.
Furino, Jr. James P.
Lin Yiqun
Lomenic Robert
Fogg and Associates LLC
Intersil America's Inc.
Lundberg Scott V.
Paladini Albert W.
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