Facsimile and static presentation processing – Facsimile – Specific signal processing circuitry
Patent
1987-08-12
1988-12-13
Groody, James J.
Facsimile and static presentation processing
Facsimile
Specific signal processing circuitry
358148, 358158, 375118, 375119, 375120, 328 55, 328 56, 328133, 307510, 307511, H04N 504
Patent
active
047914882
ABSTRACT:
A television receiver includes a phase-locked loop (PLL) which generates a clock signal having a frequency of N times the line frequency and being phase-locked to the horizontal line synchronizing signal. The clock signal produced by this PLL has a frequency which tends to jitter between N+1 and N-1 times the line frequency. To compensate for this jittering in the frequency of the clock signal, phase alignment circuitry is coupled to the PLL to align the phase of the clock signal to the horizontal drive signal produced by the PLL on the occurrence of each horizontal drive pulse. The PLL also includes a delay element which delays the horizontal drive signal applied to the phase comparator of the PLL. This delay element effectively advances the phase of the horizontal drive signal and the line-locked clock signal with respect to the horizontal sync signal to compensate for signal processing delays imparted in the generation of the horizontal drive signal and the clock signal.
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ITT Intermetall Semiconductors; "Digit 2000 VLSI Digital TV System"; pp. 113-115.
Fukazawa Kazuo
Kaneuchi Toshio
Groody James J.
Herrmann Eric P.
Nigon Kenneth N.
Parker Michael D.
Rasmussen Paul J.
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