Line decoder for memory devices

Details Line decoder for memory devices Line decoder for memory devices

1997-05-23

2000-01-25

Tokar, Michael

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

326121, 326 80, H03K 19082

Patent

active

060182555

ABSTRACT:
The row decoder includes a predecoding stage supplied with row addresses and generating predecoding signals; and a final decoding stage, which, on the basis of the predecoding signals, drives the individual rows in the array. The predecoding stage includes a number of predecoding circuits presenting two parallel signal paths: a low-voltage path used in read mode, and a high-voltage path used in programming mode. A CMOS switch separates the two paths, is driven by high voltage via a voltage shifter in programming mode, and, being formed at predecoding level, involves no integration problems.

REFERENCES:
patent: 4642798 (1987-02-01), Rao
patent: 4694430 (1987-09-01), Rosier
patent: 4791612 (1988-12-01), Yoshida
patent: 4893275 (1990-01-01), Tanaka et al.
patent: 5039882 (1991-08-01), Arakawa
patent: 5311479 (1994-05-01), Harada

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