Line decoder for memory devices

Details Line decoder for memory devices Line decoder for memory devices

1999-11-02

2000-07-25

Santamauro, Jon

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

326 80, 326 49, H03K 19082

Patent

active

060940735

ABSTRACT:
The row decoder includes a predecoding stage supplied with row addresses and generating predecoding signals; and a final decoding stage, which, on the basis of the predecoding signals, drives the individual rows in the array. The predecoding stage includes a number of predecoding circuits presenting two parallel signal paths: a low-voltage path used in read mode, and a high-voltage path used in programming mode. A CMOS switch separates the two paths, is driven by high voltage via a voltage shifter in programming mode, and, being formed at predecoding level, involves no integration problems.

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patent: 6020761 (2000-02-01), Hwang et al.
patent: 6023175 (2000-02-01), Nunomiya et al.

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