Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2005-03-01
2005-03-01
Lebentritt, Michael S. (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S301000, C257S306000, C257S758000
Reexamination Certificate
active
06861688
ABSTRACT:
A bit line configuration for contact-connecting at least one memory cell, in particular a DRAM memory cell, has bit lines disposed above the plane of the memory cell. A first bit line in a first bit line level is disposed below a second bit line in a second bit line level and the second bit line penetrates through the first bit line at at least one location of the first bit line for the purpose of producing a contact with the at least one memory cell at penetration locations. It is thus possible to provide space-saving structures, in particular sub-8F2structures.
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Heinz Hoenigschmid et al.: “A 7F2Cell and Bitline Architecture Featuring Tilted Array Devices and Penalty-Free Vertical BL Twists for 4-Gb DRAM's”,IEEE Journal of Solid-State Circuits, vol. 35, No. 5, May 2000, pp. 713-718.
Manger Dirk
Schlösser Till
Greenberg Laurence A.
Infineon - Technologies AG
Lebentritt Michael S.
Mayback Gregory L.
Stemer Werner H.
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