Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2003-03-11
2004-10-26
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S189070
Reexamination Certificate
active
06809980
ABSTRACT:
DESCRIPTION
The present invention relates to a device and a method for outputting a refresh signal for a memory cell of a semiconductor memory device, which is preferably a DRAM memory.
BACKGROUND
The memory cells of DRAM semiconductor memory devices must be periodically refreshed or updated in order to prevent a loss of data. Devices for outputting a refresh signal for a memory cell of DRAM memories are known which make it possible to adapt the frequency of the refresh signal to altered temperature conditions. However, these devices have the disadvantage that the refresh frequency can be adapted only inadequately to the refresh requirements of the memory cell.
SUMMARY
For this reason, it is an object of the present invention to provide a device and a method for outputting a refresh signal for a memory cell of a semiconductor memory device which make it possible to adapt a better control of the refresh frequency or refresh period duration in a wide temperature range.
The invention provides a device for outputting a refresh signal for a memory cell or a memory cell array of a semiconductor memory device, the device comprising:
a receiving device for receiving a variable periodic refresh input signal;
a comparison device for comparing the period duration of the refresh input signal with at least one predeterminable value;
an output device for outputting a refresh output signal in a manner dependent on the result of the comparison in the comparison device;
the output device being designed in such a way that if the period duration of the refresh input signal lies above a predeterminable maximum value, a refresh output signal with the predeterminable maximum period duration can be output, and/or
if the period duration of the refresh input signal lies below a predeterminable minimum value, a refresh output signal with a predeterminable minimum period duration can be output, and
otherwise a refresh output signal can be output whose period duration corresponds to the period duration of the refresh input signal or is proportional thereto.
The provision of a maximum and/or minimum period duration for the refresh output signal makes it possible to define an upper and/or lower period duration value for the refresh output signal. What can be achieved by the provision of an upper limit for the period duration of the refresh output signal is that a refresh signal is output to the memory cell of the semiconductor memory device within a predeterminable maximum period of time even if the refresh input signal would provide a longer period of time.
Furthermore, the lower limitation of the period duration of the refresh signal makes it possible to prevent an excessively frequent and thus unnecessary refreshing of the memory cell.
Preferably, the output device is furthermore designed for outputting a reset signal.
In a preferred embodiment, the period duration of the refresh input signal is temperature-dependent.
The provision of an upper and a lower limit for the period duration of the refresh output signal makes it possible to achieve a better adaptation of the refresh output signal to the temperature gradient of the refresh input signal. Consequently, if a temperature-dependent refresh output signal (i.e. a refresh output signal with a temperature-dependent refresh period or frequency) is output, a greater slope of the curve of the refresh output signal can be achieved since the curve limitation at the top and bottom means that safety margins are no longer necessary.
The memory cell is preferably a DRAM memory cell or a memory cell of a dynamic semiconductor memory.
The refresh input signal is preferably a clock signal.
In a preferred embodiment, the device according to the invention furthermore comprises a measuring device for determining the period duration of the refresh input signal.
The measuring device preferably comprises a counter.
Preferably, the predeterminable minimum and/or maximum period duration is generated by means of a temperature-independent periodic signal and at least one counter.
In a preferred embodiment, the counters comprise multivibrators or flip-flops.
The present invention furthermore provides a method for outputting a refresh signal for a memory cell of a semiconductor memory device, the method comprising the following steps:
reception of a variable periodic refresh input signal; comparison of the period duration of the refresh input signal with at least one predeterminable value;
outputting of a refresh output signal in a manner dependent on the result of the comparison in the comparison device;
in which case
if the period duration of the refresh input signal lies above a predeterminable maximum value, a refresh output signal with the predeterminable maximum period duration is output, and/or
if the period duration of the refresh input signal lies below a predeterminable minimum value, a refresh output signal with a predeterminable minimum period duration is output, and
otherwise a refresh output signal is output whose period duration corresponds to the period duration of the refresh input signal or is proportional thereto.
Preferably, the method furthermore comprises a step of determination of the period duration of the refresh input signal by means of a measuring device.
In a preferred embodiment, the method furthermore comprises a step of outputting of a reset signal.
REFERENCES:
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patent: 5532968 (1996-07-01), Lee
patent: 6603694 (2003-08-01), Frankowsky et al.
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P.J. Restle et al., “DRAM Variable Retention Time,” IEEE, pp. 807-810 (Apr. 1992).
E. Schrüfer,Elektrische Messtechnik“Messung elektrischer and nichtelektrischer Grössen” mit 326 Bildern and 29 Tabellen, 2., verbesserte Auflage.
Hausmann Michael
Schnabel Joachim
Fish & Richardson PC.
Infineon - Technologies AG
Nguyen Tan T.
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