Limited switch dynamic logic selector circuits

Details Limited switch dynamic logic selector circuits Limited switch dynamic logic selector circuits

2005-03-29

2005-03-29

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S095000, C326S094000

Reexamination Certificate

active

06873188

ABSTRACT:
Selector circuits and systems for single and multilevel selection within one clock cycle having a static switching factor on the output of a dynamic logic circuit. A logic device for single and multilevel selection having a dynamic logic circuit portion and a static logic circuit portion is implemented. In this way, an output logic state is maintained so long as the value of the Boolean operation being performed by the logic device does not change. Additionally, static logic elements may perform the inversions necessary to output both logic senses, mitigating the need to provide for dual-rail dynamic logic implementations. An asymmetric clock permits a concomitant decrease in the size of the precharge transistors thus ameliorating the area required by the logic element and obviating a need for keeper device.

REFERENCES:
patent: 5543731 (1996-08-01), Sigal et al.
patent: 6023179 (2000-02-01), Klass
patent: 6087855 (2000-07-01), Frederick et al.
patent: 6459316 (2002-10-01), Vangal et al.
Figure—Alliance 97, Mux Latch, one page.
Durham-IBM, Figure—The 630FP Approach to Clocking and Latching, Domino Mid-Cycle Latch (DMCL),ARL Clocking&Latch Workshop, Mar. 18-20, 1997, p. 16.
Sigal et al., “Circuit design techniques for the high-performance CMOS IBM S/390 Parallel Enterprise Server G4 microprocessor,”IBM J. Res. Develop, vol. 41, No. 4/5, Jul./Sep. 1997, pp. 489-501.

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