Limited switch dynamic logic circuit with keeper

Details Limited switch dynamic logic circuit with keeper Limited switch dynamic logic circuit with keeper

2005-11-01

2005-11-01

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S098000

Reexamination Certificate

active

06960939

ABSTRACT:
An LSDL circuit has both an output and a complementary output generated by inverting the output with an inverter logic gate. A keeper PFET is added by coupling its drain terminal to the dynamic node. The keeper PFET has its source terminal coupled to the positive power supply voltage and its gate terminal coupled to the complementary output. The output and the dynamic node may both be at a logic one when the output is a logic one from the previous evaluation cycle and the dynamic node is precharged. In this case, the complementary output is a logic zero which turns ON the keeper PFET and reinforces the precharge on the dynamic node. When the output is evaluating to a logic zero, the output will transition quickly to a logic zero. If the output is transitioning from a logic zero to a logic one, then the keeper PFET is OFF and does not affect the dynamic node.

REFERENCES:
patent: 5543731 (1996-08-01), Sigal et al.
patent: 5831990 (1998-11-01), Queen et al.
patent: 5852373 (1998-12-01), Chu et al.
patent: 6404236 (2002-06-01), Bernstein et al.
patent: 6496038 (2002-12-01), Sprague et al.
patent: 6529045 (2003-03-01), Ye et al.
patent: 6690204 (2004-02-01), Belluomini et al.
patent: 2004/0051560 (2004-03-01), Belluomini et al.

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