Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-07-07
2001-05-15
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S316000, C257S318000
Reexamination Certificate
active
06232630
ABSTRACT:
TECHNICAL FIELD
The present invention relates to non-volatile memory semiconductor devices. The present invention has particular applicability to non-volatile memory semiconductor devices having a design rule less than about 0.18 microns.
BACKGROUND ART
As the processing power of today's computers exponentially increase, attention is turned to other components of the computer system to achieve corresponding system performance gains. One such component is memory. Memory manufacturers must, accordingly, devote efforts to enhancing performance while minimizing costs. This objective becomes problematic as the demands for device miniaturization drives design rules to 0.18 microns and below. It recognized that high quality dielectrics are needed in such devices to achieve device performance both in terms of speed and longevity.
Conventional non-volatile memory semiconductor devices comprise a stacked gate structure as illustrated in FIG.
1
A. Typically, a floating gate
105
comprising polycrystalline silicon (polysilicon) is deposited onto a semiconductor substrate or epitaxial layer grown thereon (not shown) with a thin tunnel oxide layer
107
, therebetween. A dielectric layer
103
(e.g., oxide
itride/oxide, nitride/oxide, thermal oxide, HTO, etc.), is formed on floating gate
105
and a control gate
101
, such as polysilicon, is formed on dielectric layer
103
. Through manipulation of the control gate, electrons “tunnel” through the tunnel oxide to or from the floating gate. This tunnel effect is known as Fowler-Nordheim tunneling. The read/write capability of the memory cell relates to the charge state of the floating gate electrode, which is a function of the threshold voltage of the MOS transistor. The current through the tunnel oxide turns the memory cell on or off and, therefore, is instrumental in the performance of the cell.
To ensure that the appropriate amount of current flows through the tunnel oxide, conventional memory cells require that the tunnel oxide film be very thin, e.g., about 100 Å for fast operations. Unfortunately, thin tunnel oxide layers are accompanied by parasitic capacitance problems. Also, the breakdown voltage may fall below unacceptable levels. A poor breakdown voltage level may be attributed to trapping of electric charge in the oxide. This trapping effect can be mitigated through the use of higher quality oxides, which trap less charge and, thus, can withstand higher induced voltages before breakdown. In addition, the tunnel oxide layer may undergo degradation during photolithographic processing.
Basically, the engineering tradeoff is between speed of read/write operations and tunnel oxide thickness. A thinner tunnel oxide layer creates a stronger electric field between the gate and the source or drain. As a result of this intense electric field, the electrons in the thin tunnel oxide layer travel faster than they would in a thicker tunnel oxide layer. This rush of electrons translates into improved speed of the memory cell operations. However, as the tunnel oxide layer is thinned, pin holes emerge, resulting in reliability problems. Consequently, a minimal thickness must be maintained to avoid potential reliability issues. A standard test for determining oxide reliability is high temperature retention bake (HTRB).
It is recognized that high quality tunnel oxides serve a crucial role in the fabrication of semiconductor devices. A variety of methods have been developed in an attempt to optimize the engineering tradeoff.
U.S. Pat. No. 5,371,027 discloses that implantation of the tunnel oxide with a heavy ion, such as arsenic, can improve the tunnel oxide quality. During ion implantation, silicon atoms are dislodged from the underlying silicon into the tunnel oxide, producing a silicon enriched region within the tunnel oxide. The altered tunnel oxide layer subsequently assumes new tunneling characteristics. Of significance is the fact that thicker tunnel oxides can be used without compromising the level of current flow through the tunnel. That is, the current flow is comparable to that exhibited by thinner tunnel oxides. This method also avoids oxide degradation due to photolithographic processing by eliminating the need for direct contact between the tunnel oxide and photoresist layers. This method improves tunnel oxide behavior by allowing the use of a thicker oxide (about 200 Å) to achieve current flow comparable to that of a thin oxide (about 100 Å or less).
Another approach is disclosed in U.S. Pat. No. 5,591,681 and comprises oxidizing the substrate region containing a heavily-doped N+ layer. Next, an annealing process, under a gettering ambient, densities the oxide and provides doping at the oxide surface. A further oxidation step thickens the oxide. Subsequently, an NO anneal introduces nitrogen to improve the characteristics of the tunnel oxide as well as the gate. Because both floating gate and tunnel oxide are doped, doping control is more complex than the monitoring of a single layer.
In another process, as described in U.S. Pat. No. 4,789,883, the floating gate is formed of amorphous silicon instead of the conventional polysilicon. The amorphous silicon, about 2500 Å in thickness, is ion implanted with an arsenic or phosphorous dopant. Whereas the patent is concerned with in situ doping of the amorphous silicon.
There remains a need for non-volatile memory semiconductor devices having improved tunnel oxide quality, particularly for semiconductor devices having a design rule of about 0.18 microns and under.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is a non-volatile memory semiconductor device with improved tunnel oxide reliability and high voltage breakdown characteristics.
Another advantage of the present invention is a non-volatile memory semiconductor device comprising a floating gate electrode with increased charge retention.
Yet another advantage involves increased miniaturization of non-volatile memory semiconductor devices, whereby thin tunnel oxides may be utilized without compromising performance.
According to the present invention, the foregoing and other advantages are achieved in part by a semiconductor device comprising: a tunnel dielectric layer on a semiconductor substrate; a floating gate electrode comprising polycrystalline silicon on the tunnel dielectric layer; a dielectric layer on the floating gate; and a control gate on the dielectric layer, wherein the floating gate is doped with impurity atoms at a concentration of about 1×10
15
atoms/cm
3
to about 2×10
20
atoms/cm
3
.
A further aspect of the invention is a method of manufacturing a semiconductor device comprising: forming a tunnel dielectric layer on a semiconductor substrate comprising a polycrystalline silicon; forming a floating gate electrode layer comprising polycrystalline silicon and doped with impurity atoms at a concentration of about 1×10
15
atoms/cm
3
to about 2×10
20
atoms/cm
3
, on the tunnel dielectric layer; forming a dielectric layer on the floating gate; forming a control gate layer on the dielectric layer; and patterning to form a gate electrode stack comprising, sequentially, a tunnel dielectric layer, floating gate, dielectric layer and control gate.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
REFERENCES:
patent: 4603402 (1986-07-01), Cuppens et al.
patent: 4608585 (1986-08-01), Keshtbod
patent: 4789773 (1988-12-01), Cox et al.
patent: 5371027 (1994-12-
Au Kenneth Wo-Wai
Chi David H.
Pham Tuan
Ramsbey Mark T.
Sun Yu
Advanced Micro Devices , Inc.
Wojciechowicz Edward
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