Leveraging combinations of synthesis, placement and...

Details Leveraging combinations of synthesis, placement and... Leveraging combinations of synthesis, placement and...

2007-10-30

2007-10-30

Lin, Sun James (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

10903252

ABSTRACT:
Multiple optimization phases are combined to improve the performance and decrease the compilation time of user designs. An initial user design is compiled and analyzed to provide timing information. A two-pass optimization phase uses the timing information to optimize the user design. As the compilation process is repeated for the optimized user design, an incremental processing phase applies configuration information previously generated for the original user design to the corresponding portions of the optimized user design. Similarly, a selected one of a set of optimization algorithms can be applied to a modified user design, with the selection determined from an evaluation of the set of optimization algorithms on the unmodified user design. Additionally, external applications can perform one or more optimization phases on an original or modified user design. Using an illegality resolver and/or an incremental processing phase, the external applications' output can be efficiently integrated with other compilation phases.

REFERENCES:
patent: 5983277 (1999-11-01), Heile et al.
patent: 6298319 (2001-10-01), Heile et al.
patent: 7076751 (2006-07-01), Nixon et al.
patent: 2003/0149962 (2003-08-01), Willis et al.

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