Leveled non-coplanar semiconductor die contacts

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – On insulating carrier other than a printed circuit board

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Details

257703, 257701, H01L 2302, H01L 2312, H01L 3902, H01L 2348

Patent

active

052967360

ABSTRACT:
A semiconductor assembly which includes a carrier and a semiconductor die is mounted on a printed wiring board. The die includes a top active surface and a bottom active surface. The two active surfaces are non-coplanar. The carrier is made from layers of a ceramic material. Holes are formed through all but one of the layers. The layers are laminated into an integral substrate, and the substrate is fired. The holes form a cavity into but not through the substrate. The number of layers, lamination pressures, and firing parameters are all adjusted in response to the thickness of the die to insure that the height of cavity walls approximately equals the thickness of the die. Continuous metallization is applied in the cavity and on a top surface of the substrate. The die is bonded in the cavity, and conductive bumps are formed on the die and the metallization.

REFERENCES:
patent: 3617817 (1971-11-01), Kawakatsu et al.
patent: 3628105 (1971-12-01), Sarai et al.
patent: 3893159 (1975-07-01), Martin
patent: 4200880 (1980-04-01), Frey
patent: 4417392 (1983-11-01), Ibrahim et al.
patent: 4551747 (1985-11-01), Gilbert et al.
patent: 4827082 (1989-05-01), Horiuchi et al.
IBM TDM vol. 23 No. 3 Aug. 1980, C-4 Package for Programmable Read-Only Memory, S. B. Greenspan.

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