Level translator for high voltage digital CMOS process

Electronic digital logic circuitry – Interface – Supply voltage level shifting

Reexamination Certificate

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Details

C326S068000, C326S080000

Reexamination Certificate

active

06838905

ABSTRACT:
The speed of a level shifter is increased by utilizing an additional transistor to pull down the voltage on a first intermediate node, and an additional transistor to pull down the voltage on a second intermediate node. In addition, a precharge circuit is utilized to precharge the voltage on the first and second intermediate nodes to further increase the speed of the level shifter.

REFERENCES:
patent: 4656373 (1987-04-01), Plus
patent: 5444396 (1995-08-01), Soneda
patent: 5559464 (1996-09-01), Orii et al.
patent: 5559996 (1996-09-01), Fujioka
patent: 5583460 (1996-12-01), Dohi et al.
patent: 6097214 (2000-08-01), Troussel et al.
patent: 6099100 (2000-08-01), Lee
patent: 6433582 (2002-08-01), Hirano
patent: 20010011917 (2001-08-01), Kim et al.
patent: 20010013795 (2001-08-01), Nojiri
Dragan Maksimovic, Bruno Kranzen, Sandeep Dhar and Ravindra Ambatipudi, U.S. patent application No. 10/053,226, filed Jan. 19, 2002, entitled “An Adaptive Voltage Scaling Digital Processing Component and Method of Operating the Same”.
Bruno Kranzen and Dragen Maksimovic, U.S. patent application No. 10/053,227, filed Jan. 19, 2002, entitled “Adaptive Voltage Scaling Clock Generator for Use in a Digital Processing Component and Method of Operating the Same”.
Dragan Maksimovic and Sandeep Dhar, U.S. patent application No. 10/053,828, filed Jan. 19, 2002, entitled “System for Adjusting a Power Supply Lev el of a Digital Processing Component and Method of Operating the Same”.
Dragan Maksimovic, Ravindra Ambatipudi, Sandeep Dhar and Bruno Krazen, U.S. patent application No. 10/053,228, filed Jan. 19, 2002, entitled “An Adaptive Voltage Scaling Power Supply for Use in a Digital Processing Component and Method of Operating the Same”.
James T. Doyle and Dragan Maksimovic, U.S. patent application No. 10/160,428, filed Mar. 26, 2002, entitled “Meth od and System for Minimizing Power Consumption in Mobile Devices Using Cooperative Adaptive Voltage and Threshold Scaling”.
Dragan Maksimovic and James Thomas Doyle, U.S. patent application No. 10/166,822, filed Jun. 10, 2002, entitled “Serial Digital Communication Superimposed on a Digital Signal Over a Single Wire”.
Dragan Maksimovic and Sandeep Dhar, U.S. patent application No. 10/236,482, filed Sep. 6, 2002, entitled “Meth od and System for Providing Self-Calibration for Adaptively Adjusting a Power Supply Voltage in a Digital Processing System”.
Mark F. Rives, U.S. patent application No. 10/246,971, filed Sep. 19, 2002, entitled “Power Supply System and Method that Utilizes an Open Loop Power Supply Control”.
Jim Doyle and Bill Broach, Small Gains in Power Efficiency Now, Bigger Gains Tomorrow [online]. Jul. 9, 2002 [retrieved on Feb. 1, 2003]. Retrieved from the Internet: <URL: http://www.commsdesign.com/design_corner/OEG20020709S0022>. pps. 1-5.
Robert W. Erickson and Dragan Maksimovic,Fundamentals of Power Electronics,Second Edition, Kluwer Academic Publishers, 2001, pp. 333.
Krisztian Flautner, Steven Reinhardt and Trevor Mudge, Automatic Performance Setting for Dynamic Voltage Scaling, Wireless Networks, vol. 8, Issue 5, Sep. 2002, pps. 507-520, and Citation, pps. 1-3, [online]. [retrieved on Feb. 2, 2003]. Retrieved from the Internet: <URL: http://portal.acm.org/citation.cfm?id=582455.582463&coll=portal&dl=ACM&idx=J804&p . . . >.
Krisztian Flautner, Steven Reinhardt, and Trevor Mudge, Automatic Performance Setting for Dynamic Voltage Scaling [online]. May 30, 2001, [retrieved on Feb. 2, 2003]. Retrieved from the Internet: <URL http://www.eecs.umich.edu/˜tnm/papers/mobicom01.pdf>. pps. 1-12.
Texas Instruments, “Synchronous-Buck PWM Controller With NMOS LDO Controller”, TPS5110, SLVS025A—Apr. 2002, Revised Jun. 2002.
Intel XScale Core, Developer's Manual, Dec. 2000, [online], [retrieved on Feb. 2, 2003]. Retrieved from the Internet: <URL http://developer.intel.com/design/intelxscale/27347301.pdf>. pps. 1-1 through B-1.

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