Level translator circuit for power supply disablement

Electronic digital logic circuitry – Interface – Supply voltage level shifting

Reexamination Certificate

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Details

C326S068000, C326S063000, C327S333000

Reexamination Certificate

active

06861873

ABSTRACT:
A level translator circuit for use between a transmitting voltage potential circuit and a receiving voltage potential circuit is disclosed. The translator circuit comprises a logic element coupled between the transmitting circuit and the receiving circuit for translating the voltage level. The logic element includes a device which has a threshold voltage of such a level that leakage current will be minimized when the transmitting voltage potential circuit's power supply is disabled. In one embodiment, the logic element comprises a multistage inverter wherein a first stage comprises an intermediate power supply. The intermediate power supply allows for the threshold voltage to be lower. Accordingly, a level translation circuit is provided that operates effectively even when one of the voltage potential circuits is turned off. In addition, leakage current is minimized for two distinct power supplies by providing a high threshold voltage device within the level translator of the circuit to ensure that an appropriate logical level is provided at the output of the circuit.

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patent: 6750696 (2004-06-01), Shimada et al.
5-Volt Signal Level Shifter in a 3-Volt CmosCircuit, IBM Technical Disclosure Bulletin, Dec. 1989. pp. 454-55.

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