Electronic digital logic circuitry – Interface – Logic level shifting
Reexamination Certificate
2005-05-31
2005-05-31
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Interface
Logic level shifting
C327S333000
Reexamination Certificate
active
06900662
ABSTRACT:
A level translator circuit for use between a transmitting voltage potential circuit and a receiving voltage potential circuit is disclosed. The translator circuit includes a first transistor coupled to the transmitting voltage potential circuit and a clamping mechanism coupled to the first transistor. The circuit also includes a second transistor coupled to the first transistor, a higher voltage potential and the receiving voltage potential circuit. The circuit includes a third transistor coupled to the receiving voltage potential circuit, the higher voltage potential and the second transistor. Finally, the circuit includes a fourth transistor coupled to the receiving voltage potential circuit, and to a ground potential. The clamping mechanism clamps the input of the translator circuit such than an appropriate logic level is provided to the receiving voltage potential circuit and the leakage current is minimized when the transmitting voltage potential circuit is disabled. Accordingly, a level translator circuit is provided that operates effectively even when the transmitting voltage potential circuit is disabled. In addition, leakage current is minimized for the two distinct power supplies by clamping the input of the circuit such that an appropriate logical level is provided at the output of the circuit.
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5-Volt Signal Level Shifter in a 3-Volt CmosCircuit, IBM Technical Disclosure Bulletin, Dec. 1989, pp. 454-455.
Chang Daniel D.
International Business Machines - Corporation
Reid Scott W.
Sawyer Law Group LLP
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