Level translator capable of high speed operation

Details Level translator capable of high speed operation Level translator capable of high speed operation

1993-06-23

1994-11-29

Westin, Edward P.

Electronic digital logic circuitry

Interface

Logic level shifting

326 21, 327333, H03K 190175

Patent

active

053693183

ABSTRACT:
The output terminal of an ECL circuit is directly connected to the input terminal of a CMOS output circuit. The CMOS output circuit has a transistor which sets the threshold voltage of the CMOS output circuit nearly midway between ECL logic levels. A first reference voltage generating circuit has substantially the same arrangement as the CMOS output circuit and outputs a potential midway between CMOS logic levels as a first reference voltage Vref1. The first reference voltage Vref1 is made variable. A second reference voltage generating circuit has substantially the same arrangement as the ECL circuit and outputs a potential which is midway between the ECL logic levels as a second reference voltage Vref2. A comparator makes a comparison between the first and second reference voltages Vref1 and Vref2 and controls the first reference voltage generating circuit and the CMOS output circuit so that the first and second reference voltages Vref1 and Vref2 may become equal to each other.

REFERENCES:
patent: 4623802 (1986-11-01), Cline et al.
patent: 4763021 (1988-08-01), Stickel
patent: 5047657 (1991-09-01), Seevinck et al.
patent: 5105102 (1992-04-01), Shioda
patent: 5227865 (1993-07-01), Moriizumi et al.
patent: 5268872 (1993-12-01), Fujii et al.

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