Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2003-01-31
2004-08-03
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S062000, C326S021000, C327S535000, C327S333000
Reexamination Certificate
active
06771095
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to digital logic level translation and in particular to digital switching and logic level translation between one circuit having a first logic supply and another circuit having a different logic supply.
BACKGROUND OF THE INVENTION
Networks of bidirectional switches are often used to isolate or connect a particular port for parallel data interface. A switch of this type may also be used to isolate or connect a solitary data line. Devices of this type are often termed “bus switches,” especially when multiple switches are used in parallel. Not only are bus switches useful for isolating a particular device, but they may also be employed when more than one device is sharing a particular bus connection. In a configuration of this kind, bus switches can be used to create a multi-port memory, for example.
Other common applications for bus switches include live insertion (hot plug) applications. A desirable feature of the bus switch components in an application like this is that the bus switches should not interfere with bus signals, nor should the bus switch itself incur any damage. One can also envision a device of this type being used as a multiplexer or demultiplexer, where there are multiple inputs for a single output (or vice versa).
In addition, since there is more and more mixed logic level circuitry available, a bus switch is a convenient and inexpensive way to perform a logic level translation between a system utilizing a first logic supply and a second system operating with a second logic supply. As is known in the art, a high-speed, bidirectional switch having a low ON resistance can be provided by a single NMOS transistor. A single, series-connected NMOS bus switch will level-translate an input voltage level to an output voltage level that is determined by the gate voltage of the NMOS transistor minus its threshold voltage.
A circuit of this type works well when performing a level translation between 3.3V and 2.5V, or between 2.5V and 1.8V, where the supply voltage is 3.3V or 2.5V respectively. In the examples given above, the output voltage will be approximately one Vtn (NMOS transistor threshold voltage) below the first logic supply voltage, which is approximately equal to the second logic supply voltage. One must consider that using a single NMOS structure will result in clamping at the output, provided the input voltage is greater than the gate voltage minus the NMOS threshold voltage (Vgate−Vtn).
It may be desirable to connect an analog-to-digital converter (ADC) operating with a supply voltage of 3.3 volts to a digital signal processor (DSP) utilizing a 1.8 volt supply. A level translation network would allow the two devices to interface even though they are operating with different logic supplies. Failure to employ a proper level translation may subject the inputs of the DSP to voltage overstress and possible damage.
One must take into account, though, that when performing a translation between 3.3V and 1.8V, this series-connected NMOS transistor can no longer provide the desired interface between the two disparate supply voltages. Accordingly, a need arises for a level translating bus switch that can provide logic level translation even when the difference between logic supplies exceeds a particular threshold voltage, such as, for example, a single step of logic supply voltages. The desired level translating switch should be simple to construct using the latest integrated circuit processes, but should exhibit a relatively small component count, occupy minimal die area, and be conservative of power supply current.
SUMMARY OF THE INVENTION
These needs and others are satisfied by the level-translating digital switch of the present invention, in which an NMOS transistor provides switching and level translation between a first system and a second system that operate using different logic supply voltages. In a situation where the supply voltage for the first system is larger than the supply voltage for the second system, the gate of the NMOS transistor is driven by a voltage lower than the logic supply voltage of the first system.
In accordance with one aspect of the present invention, an improved digital switch includes a switching element that provides a bi-directional signal path between a first system operating with a first logic supply voltage and a second system operating with a second logic supply voltage. The improvement comprises a driver circuit providing a control voltage for the switching element, wherein the control voltage is less than the first logic supply voltage. Preferably, the switching element comprises an NMOS transistor, and the second logic supply voltage is lower in amplitude than the first logic supply voltage.
In one form of the invention, the driver circuit comprises a voltage selection portion that generates a secondary supply voltage that is less than the first logic supply voltage, and a control portion powered by the secondary supply voltage, the control portion generating a control voltage for the switching element. The voltage selection portion preferably comprises an NMOS transistor having its drain coupled to a digital switch supply voltage, and providing a secondary supply voltage at its source that is approximately one NMOS threshold voltage below the digital switch supply voltage.
In another form of the invention, the control portion comprises logic powered at least in part by the secondary supply voltage, such that the control voltage at the logic output toggles between the secondary supply voltage and a digital switch supply reference potential in response to a switch control input signal. Preferably, the logic powered at least in part by the secondary supply voltage comprises at least one inverter. In general, the digital switch supply reference potential is ground, but it may be a negative supply voltage when the control portion is configured for split supply operation.
In yet another form of the invention, the NMOS transistor drain may be coupled to the digital switch supply voltage and the NMOS transistor gate may be coupled to a voltage distinct from the digital switch supply voltage. Preferably, the voltage distinct from the digital switch supply voltage and coupled to the NMOS transistor gate is relatively independent of variations in temperature and variations in amplitude of the digital switch supply voltage.
The improved digital switch may further comprise a selection logic portion that selects between a secondary supply voltage approximately equal to the digital switch supply voltage and a secondary supply voltage that is approximately one NMOS threshold voltage less than the digital switch supply voltage in response to a selection logic control input signal.
Preferably, the selection logic portion selects a first level translation mode in response to a first selection logic control input wherein the switching element performs level translation between a first system having a logic supply voltage Vcc
1
and a second system having a logic supply voltage Vcc
2
that is approximately equal to Vcc
1
−Vtn, and the selection logic portion selects a second level translation mode in response to a second selection logic control input wherein the switching element performs level translation between a first system having a logic supply voltage Vcc
1
and a second system having a logic supply voltage Vcc
2
that is approximately equal to Vcc
1
−2*Vtn, where Vtn is approximately equal to an NMOS transistor threshold voltage.
In accordance with another aspect of the present invention, a level translating digital switch comprises a switching element that provides a bi-directional signal path between a first system operating with a first logic supply voltage and a second system operating with a second logic supply voltage, a driver circuit including a voltage selection portion comprising an NMOS transistor having its drain coupled to a digital switch supply voltage, and providing a secondary supply voltage at its source that is approximately one NMOS threshold v
Dunlea John Olan
Quill John P.
Analog Devices Inc.
Tan Vibol
Wolf Greenfield & Sacks P.C.
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