Level shifting output buffer with p channel pulldown transistors

Details Level shifting output buffer with p channel pulldown transistors Level shifting output buffer with p channel pulldown transistors

1996-06-06

1998-03-03

Hudspeth, David R.

Electronic digital logic circuitry

Interface

Supply voltage level shifting

326 63, 326 80, H03K 190185

Patent

active

057239878

ABSTRACT:
An output buffer for providing a 3.3V output from an integrated circuit designed to operate at 2.5V. A bistable level shifting circuit uses p channel pull-up and pull-down transistors where the n-wells of the transistors are coupled to the 3.3V potential. Bypass circuits are used to maintain the set/reset state and to avoid damage to the pull-down transistors. A feedforward path is used to provide biasing protection to a transistor in the output stage during a low-to-high transition.

REFERENCES:
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patent: 5321324 (1994-06-01), Hardee et al.
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patent: 5559464 (1996-09-01), Orii et al.
patent: 5570043 (1996-10-01), Churchill
patent: 5604449 (1997-02-01), Erhart et al.

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