Level shifting CMOS I/O buffer

Details Level shifting CMOS I/O buffer Level shifting CMOS I/O buffer

2000-04-06

2001-07-17

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S080000, C326S068000, C327S333000

Reexamination Certificate

active

06262599

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical field
The present invention relates generally to the field of integrated circuit design, particularly to the design of Integrated Circuits (ICs), and Application Specific Integrated Circuit (ASICs), in a system with plural or “mixed” DC voltage supplies.
2. Related Art
The field of low power integrated circuitry is a rapidly developing field of technology. Integrated circuits are continually being made smaller while simultaneously increasing both device speed and circuit density. The miniaturized devices built within and upon a semiconductor substrate are spaced very closely together and the integrated circuit density, that is, the number of transistor elements per unit of surface area, continues to increase significantly. The highest integrated circuit density is currently achieved using Field Effect Transistors (FETs).
A FET is a semiconductor device having a source, gate, and drain arranged such that when a high logic signal voltage is applied to the gate, current may pass from the source to the drain, and the voltage difference between the source and the drain approaches zero. Conversely, the FET does not allow current to pass between the source and the drain when a low logic signal voltage is applied to the transistor's gate. Complementary metal oxide semiconductor (CMOS) circuit elements further limit current usage by employing two complementary FETs (NFET and PFET) arranged gate-to-gate between the voltage supply and ground, which stops the flow of current during operation except during momentary transitions between logical states. The shorter the time that each such logical transition takes, the less current, hence power, is consumed. Therefore, power consumption and heat generation can be reduced by designing CMOS elements to “switch” states in the least amount of time possible. The length of time to require to switch a given transistor from one logical state to the other depends on both the internal characteristics of the transistor and upon the properties of the circuit that drives the gate of the transistor.
A CMOS transistor's gate operates in tandem with a parallel back-gate in a manner similar to a capacitor having a metal oxide dielectric. The larger the transistor is, the larger the area of its gate is, and the more capacitance it has. The more capacitance a transistor has, the more time it will take to “fill up” the capacitance at its gate with electric current from a given driving circuit. Similarly, the more capacitance the transistor has, the longer it will take to discharge to ground the charge stored at its gate. Therefore, smaller CMOS transistor elements are generally faster than larger CMOS transistor elements. It follows that smaller CMOS transistor elements generally consume less electrical power, and generate less heat, than larger CMOS transistor elements, and for this reason, as is more thoroughly explained below, smaller elements are generally preferred where they are otherwise functionally adequate. However, the smaller a given CMOS transistor is, the slower it will be able to fill (or empty) the gate capacitance of the next CMOS transistor or transistors which it drives. Therefore, large transistors are generally required to drive large transistors, and small transistors are generally adequate only to drive small transistors.
Generally, the fastest CMOS circuits are those which are designed to perform the required logical operation with the smallest transistors and with the fewest number of transistor elements. In designing integrated circuits, the size of a given transistor performing a particular function is generally reduced until its function would become impaired. If a given transistor can be eliminated from a known circuit design entirely without impairing the circuit's operation, that ultimate reduction of transistor size is generally considered to be an improvement in the design. In general, the more transistor elements there are in the path of a given signal, the slower that signal will propagate through the circuit to its destination, and the more power will be consumed. The necessity for level-shifting output buffers is generally due to a relentless pursuit by circuit designers of reductions of power consumption, which also may be accomplished by lowering the operating voltage applied to the transistors in the core logic, as is more thoroughly explained below.
Power consumption in electronic devices can be approximated by the equation P=VI (i.e., Power “P”=Voltage “V” times Current “I”). Power consumption is equal to the value of the DC supply voltage (e.g., “Vdd”) multiplied by the amount of current (e.g., “I”) flowing from the supply through the circuit's transistors. At any given moment in time, total current “I” consumed by a chip is generally equal to the sum of the smaller currents flowing through the numerous transistors and other circuit elements on the IC. The power consumed by a circuit in operation is transformed into heat within the circuit, which then must be continually dissipated in order to avoid thermal breakdown and failure of the circuit.
As the integrated circuit density on a chip increases, the amount of power consumed and heat generated per unit of area by the integrated circuits on the substrate increases proportionally. The integrated circuit industry has changed from TTL to CMOS in order to decrease the current consumption, thereby reducing power consumption and heat generation.
In digital CMOS systems, power consumption increases approximately proportionally with the frequency of the switching operation of the circuit. However, the minimum frequency of switching operation is usually constrained by logical and performance requirements and therefore reduction of switching frequency is not always available as a way to reduce power consumption.
To further decrease power consumption, and therefore heat generation, it is desirable that the operating voltage be reduced. Power consumption can be decreased by lowering the voltage supply (such as from five volts to three and one third volts) which also proportionally decreases the amount of current consumed. Heat generation is approximately proportional to the square of the power supply voltage at which the logic circuit is operating. Therefore, a decrease in a circuit's DC supply voltage from five volts to three volts will approximately decrease power consumption by forty percent.
The amount of heat generated is of concern to chip designers, manufactures and end-product designers because cumbersome heat sinks and customized heat-dissipating circuit packaging may become necessary to prevent a small fast chip's temperature from rising above its rated operational temperature limit. Further, the heat released is generally wasted energy, and many devices containing integrated circuits typically operate on limited stored power. One familiar example is a portable computer operating on battery power. As the heat generation in a device increases, battery life decreases. Heat itself may also adversely affect the operational life and reliability of the electronic device. Therefore, reducing the heat dissipated by a given integrated circuit is important in the design of integrated circuits and the devices into which they are incorporated.
As explained above, one way to decrease the power consumption of a circuit is to reduce the voltage at which the circuit operates. However, decreasing the operational voltage level of one circuit in a system can create compatibility problems where some other integrated circuit or other device is designed to operate at predetermined incompatible specific voltage level, or is accessible only via a bus that operates optimally at a different (e.g., higher) voltage logic level. For example, some circuits within a chip may operate at low voltage core-logic level to reduce power consumption and to interface with other chips operating at the same low voltage, while other circuits in the same chip may operate at higher voltage levels to interface with a higher logic v

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