Electronic digital logic circuitry – Interface – Logic level shifting
Reexamination Certificate
2002-12-19
2004-10-05
Le, Don (Department: 2819)
Electronic digital logic circuitry
Interface
Logic level shifting
C326S063000, C326S081000
Reexamination Certificate
active
06801053
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
Pursuant to 35 USC §119, this application claims the benefit of Taiwan Patent Application No. 91111992 filed Jun. 4, 2002.
BACKGROUND OF THE INVENTION
The present invention relates in general to a level-shifting circuit. In particular, the present invention relates to a level-shifting circuit using a single power source.
DESCRIPTION OF THE RELATED ART
Level-shifting circuits adjust the input voltage level for specific units.
FIG. 1
shows a circuit diagram of a conventional level-shifting circuit. The conventional level-shifting circuit controls a NMOS transistor by a pair of small signals Vin and XVin to lower the lower level small signal to VSS or raise the higher level small signal to VDD.
The conventional level-shifting circuit comprises PMOS transistors P
1
and P
1
′, whose sources are coupled to a first power source (9V as an example) with gates coupled to each other's drains, wherein the connection points are labels
10
and
12
. The drains of the NMOS transistors N
1
and N
1
′ are coupled to the connection points
10
and
12
. The sources of the NMOS transistors N
1
and N
1
′ are coupled to VSS, and the gates of the NMOS transistors N
1
and N
1
′ are connected to the input signals Vin and XVin, respectively. Here, the voltage level of XVin is reversed to Vin. When Vin is at a high level (3.3V as an example), XVin is at a low level. Therefore, NMOS transistor N
1
is turned on and lowers the voltage level of the connection point
10
to VSS. Thus, the PMOS P
1
′ is turned on. Since the NMOS transistor N
1
′ is turned off, the signal output from output terminal Vout is VDD. Conversely, when Vin is at a low level, XVin is at a high level (3.3V). Therefore, NMOS transistor N
1
′ is turned on and lowers the voltage level of the connection point
12
to VSS. Thus, the signal output from output terminal Vout is VSS.
To increase voltage lowering speed of the connection points
10
and
12
, NMOS transistors N
2
and N
2
′ are added. The gates of the NMOS transistors N
2
and N
2
′ are coupled to VCC, 3.3V as an example. Thus, the NMOS transistors N
2
and N
2
′ are turned on. Therefore, the voltage lowering speeds of the connection points
10
and
12
are increased when the NMOS transistors N
1
or N
1
′ are turned on. Thus, the operating speed of the level-shifting circuit is increased, and the timing error is prevented.
However, the conventional level-shifting circuit described above is not suited for low temperature poly silicon (LTPS hereinafter). LTPS products increase electron mobility to increase output current. However, the threshold voltage of the MOS transistor is also increased to about 2.5V. Thus, the NMOS transistors N
2
and N
2
′ are often left off. Therefore, the conventional level-shifting circuits meet serious RC delay in high operation frequency when applied to LTPS field.
SUMMARY OF THE INVENTION
The object of the present invention is thus to provide a level-shifting circuit using a single power source to ensure that NMOS transistors N
2
and N
2
′ are turned on to raise the output signal to VDD or VSS by a pair of inverse logic gates. Thus, the high level input signal is transformed to VDD and the low level input signal is transformed to VSS even when the voltage level of the input signal is swimming.
To achieve the above-mentioned object, the present invention provides a level-shifting circuit. The first PMOS transistor includes a first gate, a first drain, and a first source coupled to a first voltage VDD. The second PMOS transistor includes a second gate coupled to the first drain, a second drain coupled to the first gate, and a second source coupled to the first voltage VDD. The first inverse logic gate includes an output terminal and is coupled to the first drain. The second inverse logic gate includes an inverse output terminal and is coupled to the second drain. The first NMOS transistor includes a third gate coupled to the first voltage VDD, a third drain coupled to the first drain, and a third source coupled to an inverse input terminal. The second NMOS transistor includes a fourth gate coupled to the first voltage VDD, a fourth drain coupled to the second drain, and a fourth source coupled to an input terminal.
In addition, the present invention provides another level-shifting circuit. The first PMOS transistor includes a first gate, a first drain, and a first source coupled to a first voltage VDD. The second PMOS transistor includes a second gate coupled to the first drain, a second drain coupled to the first gate, and a second source coupled to the first voltage VDD. The first NMOS transistor includes a third gate coupled to the first gate, a third drain coupled to the first drain, and a third source coupled to an inverse input terminal. The second NMOS transistor includes a fourth gate coupled to the second gate, a fourth drain coupled to the second drain, and a fourth source coupled to an input terminal. The third NMOS transistor includes a fifth gate coupled to the input terminal, a fifth drain coupled to an inverse output terminal, and a fifth source coupled to a second voltage VSS. The fourth NMOS transistor includes a sixth gate coupled to the inverse input terminal, a sixth drain coupled to an output terminal, and a sixth source coupled to the second voltage VSS.
REFERENCES:
patent: 4486670 (1984-12-01), Chan et al.
patent: 6222384 (2001-04-01), Kim
patent: 6487687 (2002-11-01), Blake et al.
AU Optronics Corp.
Fish & Richardson P.C.
Le Don
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