Level-shifting circuit

Details Level-shifting circuit Level-shifting circuit

2001-09-05

2004-02-24

Tran, Anh (Department: 2819)

Electronic digital logic circuitry

Interface

Logic level shifting

C326S073000, C326S074000, C326S075000, C326S077000, C326S078000

Reexamination Certificate

active

06696858

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-268849, filed Sep. 5, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor integrated circuit device, more particularly, to a level-shifting circuit.
2. Description of the Related Art
FIG. 24
is a circuit diagram showing a conventional level-shifting circuit (4-transistor type).
As shown in
FIG. 24
, the level-shifting circuit is constituted by input side NMOS f
1
and f
3
for receiving input signals D, ND (ND is a complementary signal of D), output side PMOS f
4
cascade connected to the NMOS f
1
, and output side PMOS f
2
cascade connected to the NMOS f
3
.
The inverse operation of such level-shifting circuit is terminated by inverting drain voltage (output signal Q) of the NMOS f
3
, and drain voltage (output signal NQ; NQ is a complementary signal of Q) of the NMOS f
1
, respectively, and inverting ON/OFF of the PMOS f
4
receiving an output signal Q and the PMOS f
2
receiving an inverted output signal NQ in a gate thereof. In this inverse operation, especially in its initial stage, the drain current of the part to become ON by inversion out of the drain currents of NMOS f
1
, f
3
, is required to be sufficiently larger than the drain current of the part to become OFF by inversion out of the drain currents of PMOS f
2
, f
4
.
Specifically, in the initial stage of the inverse operation, at least the following condition (1) is required between drain current Id
1
of the NMOS f
1
(or f
3
) and drain current Id
2
of the PMOS f
4
(or f
2
) cascade connected to the drain current Id
1
:
|
Id
1
(
Vgs=Vdd−Vss
)|>|
Id
2
(
Vgs=Vss−vcc
)|  (1)
In other words, under the following condition (2), the level-shifting circuit is not operated.
|
Id
1
(
Vgs=Vdd−Vss
)|≦
Id
2
(
Vgs=Vss−vcc
)|  (2)
For example, in case the maximum voltage vdd of the input signals D, ND is reduced to the level near threshold voltage of the NMOS f
1
, f
3
, the drain current Id
1
of the NMOS f
1
(or f
3
) decreases to make it difficult to satisfy the above condition (1) and the level-shifting circuit may not be operated.
Thus, in order to have the level-shifting circuit operate sufficiently, the above condition (1) is required to be satisfied.
In case the maximum voltage Vcc (Vcc>vdd) of the output signals Q, NQ is elevated, the drain current Id
2
of the PMOS f
4
(or f
2
) increases to make it difficult to satisfy the above condition (1) similarly and the level-shifting circuit may not be operated.
Accordingly, conventionally there has been a contrivance made to enlarge element sizes of the NMOS f
1
, f
3
, and the PMOS f
2
, f
4
, in order to satisfy the condition (1) above. For example, in the NMOS f
1
, f
3
, its gate width W is increased, and in the PMOS f
2
, f
4
, its gate length L is increased. By this step, the driving capacity of the NMOS f
1
, f
3
is enhanced, and the drain current Id
1
is enlarged. On the contrary, the drain current Id
2
can be reduced.
Further, in order to satisfy the condition (1) above, a 6-transistor type level-shifting circuit as shown in
FIG. 25
is contrived.
In the 6-transistor type level-shifting circuit as shown in
FIG. 25
, PMOS f
13
or PMOS f
14
suppresses the supply of the potential to the source of PMOS f
12
or PMOS f
14
in the initial stage of the inverse operation. For this reason, this transistor may have the drain current in the initial stage of the inverse operation smaller than that of the 4-transistor type level-shifting circuit shown in FIG.
24
.
In the conventional level-shifting circuit, there may be the situation such that, in case the voltage ratio “Vcc/Vdd” between the voltage Vdd prior to the level-shifting and the voltage Vcc after the level-shifting is made larger by lowering the voltage Vdd of the input signals D, ND or elevating the voltage Vcc of the output signals Q, NQ, the level-shifting circuit fails to operate.
Accordingly, in order to dissolve this situation, contrivance is made to enlarge the element size of MOSFET which constitutes the level-shifting circuit.
However, in the field of the semiconductor integrated circuit device, there is a requirement of micronization and high integration, and there is a limit to satisfy the condition (1) described above only by the contrivance of enlarging the element size of the MOSFET.
Besides, contrivance is made of the 6-transistor type level-shifting circuit. In this 6-transistor type level-shifting circuit, in comparison with the 4-transistor type level-shifting circuit, the drain current Id
2
in the initial stage of the inverse operation can be minimized to make it easier to satisfy the above condition (1).
However, as the 6-transistor type level-shifting circuit basically only suppresses the supply of the electric current to the source of the PMOS f
4
or f
2
in the initial stage of the inverse operation, there remains a limit.
BRIEF SUMMARY OF THE INVENTION
A semiconductor integrated circuit device according to an embodiment of the present invention comprises: a level-shifting circuit configured to level-shift an input signal having a first amplitude to an output signal having a second amplitude different from the first amplitude, the level-shifting circuit having an input node in which the input signal is inputted and an output node in which the output signal is outputted; a current mirror circuit configured to charge or discharge the output node; and a switch circuit configured to operate the current mirror circuit during a period from the inversion of the input signal to the inversion of the output signal.


REFERENCES:
patent: 4150308 (1979-04-01), Adlhoch
patent: 4486670 (1984-12-01), Chan et al.
patent: 5272389 (1993-12-01), Hatada
patent: 5502405 (1996-03-01), Williams
patent: 6008667 (1999-12-01), Fahrenbruch

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