Level shifter using SR-flip flop

Details Level shifter using SR-flip flop Level shifter using SR-flip flop

2009-12-10

2011-10-04

Tran, Anh (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S068000, C326S080000

Reexamination Certificate

active

08030965

ABSTRACT:
A level shifter receives an input signal of either a first lower voltage or a first upper voltage which form a voltage pair, and level-shifts the input signal to output an output signal of either a second lower voltage or a second upper voltage. An SR flip-flop generates an output signal which is switched to the second upper voltage upon receiving a positive edge via its set terminal, and is switched to the second lower voltage upon receiving a positive edge via its reset terminal. An AND gate generates the logical AND of a feedback signal having the inverted logical level of the output signal of the SR flip-flop and the input signal, which is output to the set terminal of the SR flip-flop. A NOR gate generates the logical NOR of the feedback signal and the input signal, which is output to the reset terminal of the SR flip-flop.

REFERENCES:
patent: 6043698 (2000-03-01), Hill
patent: 6043699 (2000-03-01), Shimizu
patent: 6600357 (2003-07-01), Kirihara
patent: 7852119 (2010-12-01), Kojima
patent: 2005/0285658 (2005-12-01), Schulmeyer et al.
patent: 2009/0002027 (2009-01-01), Lee

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