Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Patent
1996-08-21
1997-12-09
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
365203, 326 62, G11C 700
Patent
active
056967225
ABSTRACT:
During a period corresponding to the former half of one cycle of a clock signal, a capacitor is charged to an intermediate potential between the respective precharged potentials of two level-shifters. Subsequently, during a period corresponding to the latter half of one cycle of the clock signal, the capacitor is connected to that one of the output nodes which shifts to a lower potential in the level-shifter on the upper stage, while a power source line is connected to the other output node which shifts to a higher potential. On the other hand, the capacitor is also connected to that one of the output nodes which shifts to the higher potential in the level-shifter on the lower stage, while the ground line is connected to the other output node which shifts to the lower potential. Consequently, there can be provided a semiconductor integrated circuit free from power dissipation that might have been caused by an internal power-source circuit. The semiconductor integrated circuit enables data transfer with a small amplitude and consumes an extremely small amount of current even when multi-bit data lines operate in parallel.
REFERENCES:
patent: 4878201 (1989-10-01), Nakaizumi
patent: 5317206 (1994-05-01), Hanibuchi et al.
patent: 5581506 (1996-12-01), Yamauchi
Matsushita Electric - Industrial Co., Ltd.
Popek Joseph A.
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