Level shifter of nonvolatile semiconductor memory

Details Level shifter of nonvolatile semiconductor memory Level shifter of nonvolatile semiconductor memory

2001-04-27

2002-11-05

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S226000

Reexamination Certificate

active

06477092

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-131388, filed Apr. 28, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a level shifter applied to a decoding circuit of a semiconductor memory, e.g., a nonvolatile semiconductor memory such as an EEPROM (Electrically Erasable Programmable Read Only Memory).
A nonvolatile semiconductor memory in which data in a plurality of memory cells are simultaneously erased is called a flash memory.
FIG. 15
shows an example of the structure of a memory cell called a stacked gate memory cell applied to a nonvolatile semiconductor memory. Referring to
FIG. 15
, a P-well
13
is formed in an N-well
12
on a P-substrate
11
. On the surface of this P-well
13
, a polysilicon floating gate
17
is formed via a gate insulating film
16
. A control gate
19
is formed on the floating gate
17
via an insulating film
18
. A source (S)
14
and a drain (D)
15
each made of an N-impurity are formed in surface regions of the P-well
13
on the both sides of the floating gate
17
and the control gate
19
.
The operation of the above memory cell will be briefly described below.
To write data in this memory cell, electrons are injected into the floating gate
17
. During this injection, 6V, for example, are applied to the drain
15
, 0V (ground potential) is applied to the P-well
13
(including the P-substrate
11
and the N-well
12
) and the source
14
, and about 10V are applied to the control gate
19
. The floating gate
17
is not connected to an external power supply. Hence, the potential of this floating gate
17
is uniquely determined by the potentials of the control gate
19
, the source
14
, the drain
15
, and the P-well
13
, in accordance with the coupling ratio of the floating gate
17
to the P-well
13
and that of the floating gate
17
to the control gate
19
. When the individual portions of the memory cell are thus set at these potentials, a strong lateral electric field (in the source-drain direction) is generated. In accordance with this electric field, hot electrons having high energy are generated. Some of these hot electrons are injected into the floating gate
17
over the barrier of the gate insulating film
16
, writing data in the memory cell.
To erase data stored in the memory cell, electrons are withdrawn from the floating gate
17
. This is done by, e.g., the following method. 10V, for example, are applied to the N-well
12
, the P-well
13
, and the source
14
, and −7V are applied to the control gate
19
. As a consequence, a large electric field of 10 MV/cm or more is applied to the gate insulating film
16
. This large electric field causes an F-N (Fowler-Noldheim) current (tunnel current) to flow through the gate insulating film
16
. Accordingly, electrons are emitted from the floating gate
17
to the P-well
13
and the source
14
, erasing data in the memory cell.
Data stored in the memory cell is read out as follows. As described above, the potential of the floating gate of the written memory cell differs from that of the floating gate of the erased memory cell. That is, electrons are built up in the floating gate
17
of the written memory cell. Therefore, to form an N-channel immediately below the floating gate
17
by applying a voltage to the control gate
19
, the floating gate
17
must be given a positive electric charge larger than when the channel is to be formed in the erased memory cell. More specifically, the potential (to be referred to as VREAD hereinafter) of the control gate
19
is so controlled as not to form a channel in the written memory cell but to form a channel in the erased memory cell. Accordingly, by giving an appropriate potential between the drain and source and setting the potential of the control gate
19
at VREAD, e.g., 5V, a channel is formed in the erased memory cell whereas no channel is formed in the written memory cell. Consequently, an electric current determined by the potential difference between the drain and source and the potential of the floating gate flows through the erased memory cell, similar to a common N-channel transistor. Data in the memory cell can be read out by detecting whether an electric current flows through the memory cell when VREAD is thus applied to the control gate of the memory cell.
FIG. 16
shows the configuration of a nonvolatile semiconductor memory. An input circuit
21
receives an address control signal. A control circuit
22
decodes the signal from the input circuit
21
and supplies a control signal to other circuits. A memory cell array
23
has memory cells (not shown) arrayed into m rows×n columns. A boosting circuit
24
generates a high voltage for a data write, erase, and read to the memory cells arranged in the memory cell array
23
. A row decoder
25
selects a word line (not shown) arranged in the memory cell array
23
, in accordance with the output signal from the control circuit
22
. A column decoder
26
selects a bit line arranged in the memory cell array
23
, in accordance with the output signal from the control circuit
22
. A source and well decoder
27
supplies the potential of the P-well and the potential of the source to the memory cell array
23
, in accordance with the output signal from the control circuit
22
. A write circuit
28
performs data write and verification. A read circuit
29
discriminates data read out from a selected memory cell during data read. An output circuit
30
is connected to the read circuit
29
and outputs data read out by the read circuit
29
.
FIG. 17
shows details of the arrangement of the memory cell array
23
shown in FIG.
16
. For the sake of descriptive simplicity, memory cells MC are arranged into a matrix of 3 rows×4 columns in a P-well (not shown). The control gates of memory cells MC belonging to the same rows are connected to corresponding word lines WL
0
to WL
2
. The drains of memory cells belonging to the same columns are connected to corresponding bit lines BL
0
to BL
3
. Also, the source of each memory cell MC is connected to a source line SL, and source lines SL in the same P-well are connected together.
In data write and read, a specific memory cell is selected by a word line WLm (m=0 to 2) selected by the row decoder
25
and a bit line BLn (n=0 to 3) selected by the column decoder
26
. Data write or read is performed for this selected memory cell. Data erase is performed for the m×n memory cells arranged in the same P-well at the same time.
FIG. 18
shows an example of the row decoder
25
. An address converter
42
receives a plurality of row-select internal address signals
41
generated via the input circuit
21
and the control circuit
22
, and activates an address-select line
45
in accordance with these internal address signals
41
. The potential of the word line WLm is different from the power supply voltage (Vcc) in any of data read, write, and erase. Hence, the address-select line
45
is connected to a level shifter
43
, and the potential of this address-select line
45
is converted into a required potential by the level shifter
43
. The output voltage from this level shifter
43
is supplied to a buffer circuit
44
. A voltage whose waveform is shaped by this buffer circuit
44
is supplied to the word line WLm.
FIG. 19
shows another example of the row decoder
25
. In this example, internal address signals are divided into two systems. That is, a plurality of row-select internal address signals
41
a
and a plurality of row-select internal address signals
41
b
, generated via the input circuit
21
and the control circuit
22
, are supplied to first address converters
42
a
and
42
b
, respectively. In accordance with these internal address signals
41
a
and
41
b
, the first address converters
42
a
and
42
b
activate address-select lines
45
a
and
45
b
, respectively. These address-select lin

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