Level shifter having low duty cycle distortion

Details Level shifter having low duty cycle distortion Level shifter having low duty cycle distortion

2011-06-07

2011-06-07

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Interface

Logic level shifting

C327S333000

Reexamination Certificate

active

07956642

ABSTRACT:
A level shifter includes an inverting circuit, a cross-coupled level shifting latch, and a SR logic gate latch. The first and second outputs of the level shifting latch are coupled to the set (S) and reset (R) inputs of the SR latch. The inverting circuit, that is powered by a first supply voltage VDDL, supplies a noninverted version of an input signal onto a first input of the level shifting latch and supplies an inverted version of the input signal onto a second input of the level shifting latch. A low-to-high transition of the input signal resets the SR latch, whereas a high-to-low transition sets the SR latch. Duty cycle distortion skew of the level shifter is less than fifty picoseconds over voltage, process and temperature corners, and the level shifter has a supply voltage margin of more than one quarter of a nominal value of VDDL.

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International Search Report—PCT/US08/068247, International Search Authority—European Patent Office, Sep. 15, 2008.
Written Opinion—PCT/US08/068247, International Search Authority—European Patent Office, Sep. 15, 2008.

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