Electronic digital logic circuitry – Interface – Logic level shifting
Reexamination Certificate
2000-03-02
2001-12-11
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Logic level shifting
C326S063000, C326S080000, C326S083000
Reexamination Certificate
active
06329841
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to level shifter circuitry and more particularly, it relates to an improved level shifter circuit for use with an extremely low power supply voltage.
As is generally well-known, digital logic circuits are widely used in the areas of electronics and computer-type equipment. However, the various digital logic circuits that must communicate with one another may have different power supply voltages. For example, a first circuit that operates with logic levels between 0 V (L) and 2.0 V (H) may need to communicate with a second circuit that operates with logic levels between 0 V (L) and 3.3 V (H). Thus, when a first digital logic circuit of one power supply voltage is required to interface with a second digital logic circuit of another power supply voltage there is typically needed a voltage conversion or translation between the two different power supplies so that they will be compatible with each other and not drain static current. A level shifter circuit is provided to perform this function.
In
FIG. 1
, there is shown a schematic circuit diagram of a prior art level shifter circuit
10
which may be used to perform a voltage conversion. The level shifter circuit
10
is comprised of a pass N-channel MOS transistor N
1
; pull-up P-channel MOS transistors P
1
, P
2
; and pull-down N-channel MOS transistors N
4
, N
5
. The first P-channel transistor P
1
has its source connected to the source of the second P-channel transistor P
2
and to a high voltage HV, which is typically at approximately VCC−+10 volts The drain of the transistor P
1
is connected to the gate of the transistor P
2
and to the source of the pass transistor N
1
. The gate of the transistor P
1
is connected to the drain of the transistor P
2
at a node A, which is connected to an output terminal OUT.
The pass transistor N
1
has its drain connected to an input terminal IN for receiving an input signal and to the gate of the pull-down transistor N
5
. The gate of the transistor N
1
is connected to a first power supply potential VCC, which is typically at +2.0 V. The pull-down transistor N
4
has its drain connected also to the node A and to the output terminal OUT. The pull-down transistor N
5
has its drain connected to the source of the transistor N
4
and its source connected to a second power supply or ground potential VSS (zero volts). The n-type substrate of the P-channel transistors P
1
, P
2
is tied to its source and to the high voltage NV.
In operation, when the input signal at the input terminal IN is at 0 volts the pull-up transistor P
2
will be turned ON and the transistors P
1
and N
5
will both be turned OFF. As a result, the level shifter circuit
10
will produce a voltage level of HV (i.e., +9 V) at the output terminal OUT. On the other hand, when the input signal at the input terminal IN is at VCC (i.e., 2.0 V), the transistors N
5
and P
1
will both be turned ON and the transistor P
2
will be turned OFF. Thus, the level shifter circuit
10
will provide a voltage level of 0 volts at the output terminal OUT.
However, this existing prior art level shifter circuit
10
suffers from the principal disadvantage that it will fail or not operate when the power supply voltage VCC is reduced down to an extremely low voltage, such as +1.0 volts which is equivalent to the threshold voltage of the P-channel MOS transistors P
1
, P
2
and HV=VCC. In view of the trend for deep-submicron CMOS technology, lower and lower power supply voltages VCC are being used. Thus, as the power supply voltage VCC is made lower to be near or below the threshold voltage of the P-channel transistors P
1
, P
2
and the high voltage HV is made to be equal to the supply potential VCC, neither of the pull-up transistors P
1
or P
2
will be able to be turned ON and consequently, the node A or output terminal OUT will be left floating.
Further, as the thickness of the gate oxides for forming the CMOS transistors are being made thinner and thinner in the CMOS technology, such as 60 Å (angstrom) or below, a voltage difference higher than about +2.4 V-+2.5 V applied across the gate and the bulk of the transistor device will cause a breakdown in the gate oxide to occur, thereby creating a failure. For example, when the input signal of 0 volts is applied to the gate of the transistor P
2
in
FIG. 1
, the level shifter circuit
10
will generate a voltage level of HV volts at the output terminal OUT. As will, be noted, there will be created a voltage difference of HV between the drains and the gates of the P-channel transistors P
1
, P
2
. If the transistors P
1
, P
2
were made of thin oxide; this will cause a breakdown of the thinner gate oxides.
Therefore, it would be desirable to provide an improved level shifter circuit which is designed to be capable of operating with an extremely low power supply voltage. Further, it would be expedient that the level shifter circuit be able to prevent the breakdown of the gate oxide in all of the transistors.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide an improved level shifter circuit for use with an extremely low power supply voltage which has been traditionally unavailable.
It is an object of the present invention to provide an improved level shifter circuit which is designed to operate with an extremely low power supply voltage.
It is another object of the present invention to provide an improved level shifter circuit which prevents the breakdown of the gate oxide in all of the transistors.
It is still another object of the present invention to provide an improved level shifter circuit which includes a secondary path circuit for passing a high voltage to an output terminal when the high voltage is lowered to be equal to a power supply voltage of +1.0 volts.
In a preferred embodiment of the present invention, there is provided a level shifter circuit for use with an extremely low power supply voltage which includes an input terminal for receiving an input signal having first and second levels and an output terminal for providing an output signal having third and fourth levels. There is provided a first power supply voltage having the extremely low power supply voltage, a second power supply voltage having a ground potential, and a third power supply voltage having a high voltage.
There is provided first and second PMOS transistors. The first PMOS transistor has its source connected to the source of the second PMOS transistor, its drain connected to the gate of the second PMOS transistor at an internal node, and its gate connected to the drain of the second PMOS transistor and to the output terminal.
There are provided first and second NMOS transistors. The first NMOS transistor has its drain connected to the drain of the second PMOS transistor and to the output terminal. The first NMOS transistor has its source connected to the drain of the second NMOS transistor and its gate connected to the first power supply voltage. The second NMOS transistor has its gate connected to receive the input signal and its source connected to the ground potential. A third NMOS transistor has its drain connected to the input terminal, its gate connected to the first power supply voltage, and its source connected to the internal node.
A secondary path circuit is responsive to the input signal for transferring the high voltage to the output terminal when the high voltage is lowered to be equal to the first power supply voltage. The secondary path circuit includes a fourth NMOS transistor, a third PMOS transistor, and a fifth NMOS transistor connected in series and interconnected between the high voltage and the output terminal and an inverter.
REFERENCES:
patent: 4574273 (1986-03-01), Atsomi et al.
patent: 5136190 (1992-08-01), Chern et al.
patent: 5266848 (1993-11-01), Nakagome et al.
patent: 5321324 (1994-06-01), Hardee et al.
patent: 5465069 (1995-11-01), Boiron et al.
patent: 5602495 (1997-02-01), Lou
patent: 5646550 (1997-07-01), Campball
Advanced Micro Devices , Inc.
Chin Davis
Paik Steven S.
Tokar Michael
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