Level shifter for an input/output bus in a CMOS dynamic ram

Details Level shifter for an input/output bus in a CMOS dynamic ram Level shifter for an input/output bus in a CMOS dynamic ram

1987-11-25

1989-08-22

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

365203, G11C 700

Patent

active

048602574

ABSTRACT:
A level shifter for an input/output bus in a CMOS dynamic RAM employs a first and second PMOS transistor. The first and second PMOS transistors are connected to and cut off a current flow between a pair of input/output lines and a pair of input/output sense amplifier input lines which are connected to input/output sense amplifiers. First and second inverters are included for each of the first and second PMOS transistors, each inverter has an input for receiving a signal for a selection of the input/output line pair and has a respective output which is connected to a corresponding gate and drain of the first and second PMOS transistors.

REFERENCES:
patent: 4618785 (1986-10-01), Van Tran

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