Level shifter circuit constituted of E and I type transistors an

Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit

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36523006, 307475, G11C 700

Patent

active

053413342

ABSTRACT:
An input terminal inputs an input signal oscillating between a first power source voltage and second power source voltage according to a selected mode and a non-selected mode. An output terminal delivers a signal oscillating between the first and second power source voltages and a third power source voltage according to voltage conversion and non-voltage conversion. An N-channel E type transistor of a positive threshold voltage has a source electrode and a drain electrode connected between the input terminal and the output terminal and a gate electrode supplied with the second power source voltage. An N-channel I type transistor of a neutral threshold voltage has a source electrode and a drain electrode connected between the input terminal and the output terminal and a gate electrode supplied with a control signal oscillating between the first power source voltage and the second power source voltage, the control signal determining whether or not a voltage conversion is made. A charge pump circuit is connected to the output terminal and operative with the first, second and third power source voltages such that the charge pump circuit is rendered an active state only when the voltage conversion is mode. A predetermined number of level shifter circuits having an arrangement as set out above are connected between row and column decoders of an EEPROM on one hand and a cell matrix array on the other hand.

REFERENCES:
patent: 4642482 (1987-02-01), Kasperkovitz et al.
patent: 5031149 (1991-07-01), Matsumoto et al.
patent: 5058063 (1991-10-01), Wada et al.
patent: 5065361 (1991-11-01), Yoshizawa et al.
patent: 5202855 (1993-04-01), Morton

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