Level shifter circuit and semiconductor memory device using...

Details Level shifter circuit and semiconductor memory device using... Level shifter circuit and semiconductor memory device using...

2007-09-25

2007-09-25

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S185230

Reexamination Certificate

active

11330143

ABSTRACT:
A level shifter circuit comprises a first output MIS transistor of a first conductivity, and a second output MIS transistor of a second conductivity type having a second threshold voltage. The former has a first threshold voltage, wherein the output voltage is positively fed back to a gate terminal and the power supply voltage is applied to a first terminal to generate a first voltage at a second terminal. In the latter, the first voltage is applied to a first terminal and a second voltage is applied to a gate terminal to control conduction to generate the output voltage at a second terminal. The first and second charge type MIS transistors and the discharge MIS transistor are connected between the first terminal and gate terminal of the second output MIS transistor to charge or discharge the potential of the gate terminal of the second output MIS transistor.

REFERENCES:
patent: 5031149 (1991-07-01), Matsumoto et al.
patent: 6101126 (2000-08-01), Chung et al.
patent: 6160735 (2000-12-01), Hirano
patent: 6166969 (2000-12-01), Song et al.
patent: 6512253 (2003-01-01), Watanabe et al.
patent: 6621735 (2003-09-01), Nakamura et al.
patent: 2000-91546 (2000-03-01), None

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