Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
2000-05-02
2001-10-16
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S068000, C326S080000
Reexamination Certificate
active
06304105
ABSTRACT:
BACKGROUND OF THE INVENTION
(1). Field of the Invention
The present invention relates to a level shifter circuit for use in a semiconductor integrated circuit device in which circuits are operated by different voltages, in particular relates to a level shifter circuit which shifts the level of the signal output from a low-voltage operating circuit and outputs a level-shifted signal to a high-voltage operating circuit.
(2). Description of the Prior Art
FIG. 1
is a circuit diagrams showing a configurational example of a conventional level shifter circuit (c.f. Japanese Patent Application Laid-Open Hei 7 No. 193488).
This level shifter circuit includes low-voltage operating inverters INV
1
and INV
2
, a high-voltage operating inverter INV
3
, N-channel MOS (to be abbreviated as NMOS hereinbelow) transistors NT
1
, NT
2
, NT
3
and NT
4
and P-channel MOS (to be abbreviated as PMOS hereinbelow) transistors PT
1
and PT
2
. The output from low-voltage operating inverter INV
1
, the input to low-voltage operating inverter INV
2
, the gates of NMOS transistors NT
1
and NT
3
are joined. The output from low-voltage operating inverter INV
2
is connected to the gates of NMOS transistors and NT
2
and NT
4
. The input to high-voltage operating inverter INV
3
, the drains of NMOS transistors NT
2
and PMOS transistors PT
2
, the gate of PMOS transistor PT
1
and the source of NMOS transistor PT
3
are joined. The drains of NMOS transistor NT
1
and PMOS transistor PT
1
and the gate of PMOS transistor PT
2
and the source of NMOS transistor NT
4
are joined. The sources of PMOS transistors PT
1
and PT
2
and the drains of NMOS transistors NT
3
and NT
4
are connected to the power feed line from a high-voltage power source. The input to low-voltage operating inverter INV
1
forms an input signal terminal Vin
1
while the output from high-voltage operating inverter INV
3
forms an output signal terminal Vout
1
.
Next, the operation of the thus configured level shifter circuit will be described. When a signal which transits from a VSS level (to be referred to as ‘the L-level’ hereinbelow) to a VDD
1
level (to be referred to as ‘the H-level’ hereinbelow) is supplied from a low-voltage operating circuit to input signal terminal Vin
1
, the output signal from low-voltage operating inverter INV
1
transits from the H-level to the L-level. With this transition, the ON-state resistance of NMOS transistor NT
1
and that of NT
3
gradually increase, so the source-drain voltage of NMOS transistor NT
1
and that of NT
3
increase. At almost the same time, the output signal from low-voltage operating inverter INV
2
transits from the L-level to the H-level so that NMOS transistors NT
2
and NT
4
become activated with their resistances gradually becoming lowered and hence the voltages of NMOS transistors NT
2
and NT
4
between source and drain become lowered. The activation of NMOS transistor NT
4
raises the potential at the gate of PMOS transistor PT
2
to a midway voltage so that the ON-state resistance rises. This causes NMOS transistor NT
2
to lower the potential at a node n
2
. Simultaneously, the lowered potential at node n
2
lowers the ON-state resistance of PMOS transistor PT
1
while raising the potential at a node nl. When input signal terminal Vin
1
from the low-voltage operating circuit definitely reaches the H-level, NMOS transistors NT
1
and NT
3
are turned off, NMOS transistors NT
2
and NT
4
are turned on, PMOS transistor PT
1
is turned on, and PMOS transistor PT
2
is turned off. Thereby the output signal terminal Vout
1
to the high-voltage operating circuit becomes stabilized and set at a VDD
2
level (to be referred as ‘the HH level’).
On the other hand, when a signal which transits from the L-level to the H-level is supplied from the low-voltage operating circuit to input signal terminal Vin
1
, the output signal from low-voltage operating inverter INV
1
transits from the L-level to the H-level. With this transition, the ON-state resistance of NMOS transistor NT
1
and that of NT
3
gradually become lowered, so the source-drain voltage of NMOS transistor N
1
and that of NT
3
become lowered. At almost the same time, the output signal from low-voltage operating inverter INV
2
transits from the H-level to the L-level so that NMOS transistors NT
2
and NT
4
become inactive with their resistances gradually increasing and hence the voltages of NMOS transistors NT
2
and NT
4
between source and drain increase. The activation of NMOS transistor NT
3
raises the potential at the gate of PMOS transistor PT
1
to a midway voltage so that the ON-state resistance rises. This causes NMOS transistor NT
1
to lower the potential at a node n
1
. Simultaneously, the lowered potential at node n
1
lowers the ON-state resistance of PMOS transistor PT
2
while raising the potential at a node n
2
. When input signal terminal Vin
1
from the low-voltage operating circuit definitely reaches the L-level, NMOS transistors NT
1
and NT
3
are turned on, NMOS transistors NT
2
and NT
4
are turned off, PMOS transistor PT
1
is turned off, and PMOS transistor PT
2
is turned on. Thereby the output signal terminal Vout
1
to the high-voltage operating circuit becomes stabilized and set at the L-level.
The above conventional level shifter circuit, however, suffers from the following drawback. That is, in the conventional level shifter circuit, for example, when a signal changing from the L-level to the H-level is supplied from the low-voltage operating circuit to input signal terminal Vin
1
, the output signal from low-voltage operating inverter INV
1
changes from the H-level to the L-level while the output signal from low-voltage operating inverter INV
2
changes from the L-level to the H-level. Upon these transitions, the change of the output signal from low-voltage operating inverter INV
2
lags behind the change of the output signal from low-voltage operating inverter INV
1
. Therefore, NMOS transistors NT
1
, NT
2
, NT
3
and NT
4
and PMOS transistors PT
1
and PT
2
are temporarily turned off, causing potential instability at nodes n
1
and n
2
and hence producing difficulties in operating the level shifter at high speeds. The same drawback occurs when a signal changing from the H-level to the L-level is supplied from the low-voltage operating circuit to input signal terminal Vin
1
.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a level shifter circuit capable of solving the above drawback in the conventional level shifter circuit.
In order to achieve the above object, the present invention is configured as follows:
In accordance with the first aspect of the present invention, a level shifter circuit that receives the output signal from a low-voltage operating circuit and outputs a signal to a high-voltage operating circuit, includes:
a first inverter receiving at the input terminal thereof a signal output from the low-voltage operating circuit and being operated by the low-voltage power source;
a resistance divider circuit configured of a connected circuit of a plurality of MOS transistors, each having a predetermined ON-state resistance and including ON/OFF controllable MOS transistors in accordance with the output signal from the first inverter, the connected circuit being disposed between the high-voltage power source and the ground potential so as to produce an output signal of a predetermined level in accordance with the output signal from the first inverter; and
a second inverter receiving the output signal from the resistance divider circuit at the input terminal thereof and being operating by the high-voltage power source.
In accordance with the second aspect of the present invention, the level shifter circuit having the above first feature is characterized in that the resistance divider circuit include: a first N-channel MOS transistor connected at the gate and drain thereof to the high-voltage power source; a second N-channel MOS transistor, connected at the gate thereof to the high-voltage power source, connected at the drain th
Sharp Kabushiki Kaisha
Tokar Michael
Tran Anh Q.
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