Electronic digital logic circuitry – Interface – Logic level shifting
Reexamination Certificate
1998-10-05
2001-04-24
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Logic level shifting
C326S081000, C365S189110
Reexamination Certificate
active
06222384
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a level shifter circuit, and paticular to a level shifter circuit which is capable of outputting at least three different voltage levels.
2. Background of the Related Art
FIG. 1
illustrates a voltage level translator according to the background art. An inverter INV
11
inverts an input signal IN. An NMOS transistor NM
11
includes a gate connected for receiving an output signal from the inverter INV
11
, a source connected to a ground voltage VSS, and a drain connected with a node B. An NMOS transistor NM
12
includes a gate connected to receive an externally applied voltage VCC, a source connected to a node B, and a drain connected to a node C. An NMOS transistor NM
13
includes a gate connected to receive the externally applied voltage VCC, a source receiving an output signal from the inverter INV
11
, and a drain connected to a node D. An NMOS transistor NM
14
includes a gate receiving a supply voltage VCCp, a source connected to the node D, and the drain connected to the node E. An NMOS transistor NM
15
includes a gate receiving the supply voltage VCCp and a source receiving the externally applied voltage.
A PMOS transistor PM
11
includes a gate connected to a node E, and a drain connected to the node C, wherein the supply voltage VCCp is supplied to the source and the substrate. A PMOS transistor PM
12
includes the gate connected to the node C, and a drain connected to the node E, wherein the supply voltage VCCp is supplied to the source and the substrate, respectively. A PMOS transistor PM
13
includes a gate connected to the node C, and a drain connected to a node O, wherein the supply voltage VCCp is supplied to the
5
source and the substrate. A PMOS transistor PM
14
includes a gate connected to the node E, a source connected to the drain of the PMOS transistor PM
13
, and a drain connected to the drain of the NMOS transistor NM
15
, wherein the supply voltage VCCp is applied to the substrate. An output signal OUT is outputted at the node O.
As shown in
FIGS. 2A through 2G
, when the input signal IN is triggered from a high level to a low level, the signal transits from the low level to high level at the node A which is an output terminal of the inverter INV
11
. Therefore, the NMOS transistor NM
11
is turned on, and the level of the signal becomes a low level a the node B. Since the NMOS transistor NM
12
is always turned on, the level of the signal becomes a low level at the node C.
At the node D, the level of the signal is within a range of VCC-Vt by the NMOS transistor NM
13
. When the level of the signal becomes a low level at the node C, the PMOS transistor PM
12
is activated, such that the signal level at the node E is increased up to the supply voltage VCCp, and the signal level transits to the level of VCCp-Vt, where Vt is a threshold voltage of about 0.7 volts. Therefore, the PMOS transistors PM
11
and PM
14
are turned off. Since the signal level is a low level at the node C, the PMOS transistor PM
13
is turned on, and the signal level at the node O becomes the supply voltage VCCp. Namely, the output signal OUT level becomes the supply voltage VCCp.
Thereafter, when the input signal IN transits from the low level to the high level, the signal level transits from the high level to the low level at the node A. Thereafter, the NMOS transistor NM
11
is turned off, and the signal level transits to a low level at the node D. Therefore, the signal level becomes a low level at the node E, and the PMOS transistor PM
11
is activated. The signal level at the node C is increased to the supply voltage VCCp, and the PMOS transistors PM
12
and PM
13
are turned off. Since the signal level is low at the node E, the PMOS transistor PM
14
is activated. Further, since the NMOS transistor NM
15
is originally turned on, the output signal OUT becomes an externally applied voltage VCC level at the node O.
In order to use the voltage level translator as a transfer gate driver in a memory circuit such as the DRAM, the output signal OUT level is the externally applied voltage VCC or VCCp. However, in the case of the selected block, the output level should be able to transit to the ground voltage VSS. In order to output the ground voltage VSS, additional circuit needs to be provided, which is disadvantageous for reducing the layout area.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a level shifter circuit which overcomes at least the aforementioned problems.
It is another object of the present invention to provide a three-phase voltage level without additional circuits or components compared to the background art.
It is another object of the present invention to provide an improved level shifter circuit for use as a transfer gate driver.
It is another object of the present invention to reduce power consumption.
It is another object of the present invention to provide a shifter circuit having high operation speed.
It is a further object of the present invention to reduce layout area.
To achieve the above objects, in a whole or in parts, there is provided a level shifter circuit which includes an inverter for inverting an input signal, a first NMOS transistor a gate of which receives an input signal inverted by the inverter, a source of which is connected with a ground voltage VSS, and a drain of which is connected with a node B′, a second NMOS transistor a gate of which receives a first input signal, a source of which is connected with a ground voltage VSS, and a drain of which is connected with a node A′, a third NMOS transistor a gate of which receives an externally applied voltage VCC, a source of which is connected with the node A′, and a drain of which is connected with a node D′, a first PMOS transistor a gate of which is connected with the node D′, and a drain of which is connected with the node C′ wherein a source of which and a substrate receives a raised voltage VPP, a second PMOS transistor a gate of which is connected with the node C′, and a drain of which is connected with the node D′ wherein a source of which and a substrate receives the raised voltage, a third PMOS transistor a gate of which is connected with the node C′, and a drain of which is connected with a node O′ wherein a source of which and a substrate receive a raised voltage VPP, a fourth NMOS transistor a gate of which is connected with the node C′, a drain of which is connected with the node O′, and a source of which receives a second input signal, and a fourth PMOS transistor a gate of which is connected with the node D′, a source of which is connected with the node O′, and a drain of which receives the second input signal.
The present invention may also be achieved in parts and in a whole by a level shifter comprising: a pair of cross-coupled transistors coupled for receiving a first potential; a plurality of transistors coupled between the pair of cross-coupled transistors and a second potential; and an output unit having a pull-down switch for providing an output signal of one of first, second and third potentials and coupled to the pair of cross-coupled transistor and the plurality of transistors, the third potential having a potential between the first and second potentials.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
REFERENCES:
patent: 5394374 (1995-02-01), Ishimura et al.
patent: 5412604 (1995-05-01), Fukuda et al.
patent: 5444408 (1995-08-01), Merritt
patent: 5521869 (1996-05-01), Ishimura et al.
patent: 5528173 (1996-06-01), Merritt et al.
patent: 5670905 (1997-09-01), Keeth et al.
Chang Daniel D.
Fleshner & Kim LLP
Hyundai Electronics Industries Co,. Ltd.
Tokar Michael
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