Electronic digital logic circuitry – Interface – Logic level shifting
Reexamination Certificate
1999-08-11
2001-04-24
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Logic level shifting
C326S063000
Reexamination Certificate
active
06222385
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a level shifter, and more particularly, to a level shifter circuit which can make an efficient level shift to level up or level down according to a change of a digital logic characteristic.
2. Background of the Related Art
Either level up or down by the level shifter is determined according to a digital logic of the level shifter input/output, according to which a level shifter circuit is designed. A related art level shifter will be explained with reference to the attached drawings.
FIG. 1
illustrates a system of a related art level shifter circuit, and
FIG. 2
illustrates a graph showing a related art voltage transfer characteristic.
Referring to
FIG. 1
, the related art level shifter is provided with a first NMOS transistor MNI having a gate for receiving a digital logic signal, an inverter buffer INI for receiving the digital logic signal and determining an output switching point for the digital logic signal, a second NMOS transistor MN
2
having a gate for receiving an output from the inverter buffer IN
1
, and a first and a second PMOS transistors MP
1
and MP
2
having gates for receiving outputs from drains of the first and second NMOS transistors MN
1
and MN
2
serving as active loads for the first and second NMOS transistors MN
1
and MN
2
.
The operation of the related art level shifter will be explained. The operation of the level shifter can be known efficiently when a state of an output voltage Vout, i.e., an output state of an input voltage Vin provided to a gate of the first NMOS transistor MN
1
after being swept is reviewed. That is, the voltage transfer characteristics are as follows.
Referring to
FIG. 2
, when the input voltage Vin is at low, the output voltage is also at low. In this state, if the input voltage is increased, a Vgs of the first NMOS MN
1
is increased, causing a current flowing through the first NMOS transistor MN
1
to increase. Though the current flowing through the first NMOS transistor MN
1
is increased, the output voltage shows no substantial increase compared to a prior voltage. There is no substantial increase in the output voltage Vout because an output from the inverter buffer IN
1
shows no substantial change if an input to the inverter buffer IN
1
is increased over the low level(a level of the Vin received presently), which output is connected to the gate of the second NMOS transistor MN
2
thereby causing no substantial change in the current flowing through the second NMOS transistor NM
2
. If the input keeps increasing from this state to a state higher than the low level but lower than a high level, the inverter buffer IN
1
is operative in a transition region, decreasing the current flowing through the second NMOS transistor MN
2
. If the current flowing through the second NMOS transistor MN
2
is decreased, the Vgs voltage of the second NMOS transistor MN
2
is lowered to boost the output voltage Vout. That is, the decrease of Vgs of the first PMOS transistor MP
1
further decreases the current flowing through the first PMOS transistor MP
1
, that further decreases a voltage between the drain-source of the first NMOS transistor MN
1
. When this case is occurred, the current flowing through the second PMOS transistor MP
2
is further increased, accelerating increase of the output voltage faster to a high voltage. Thus, the first PMOS transistor MP
1
and the second PMOS transistor MP
2
vary output voltage levels with logic state changes of the input voltage Vin in the level shifter circuit.
However, the related art level shifter circuit has the following problem because level up or down is determined according to a digital logic of the level shifter input/output, according to which the level shifter circuit is designed. That is, if input and output digital logic characteristic is changed from a level up to a level down or vice versa, the present level up shifter(or a level down shifter) should be re-designed.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a level shifter circuit that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a level shifter circuit which can make an efficient level shift operation to level up or level down according to a change of a digital logic characteristic.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the level shifter circuit, for making an efficient level shift to level up or level down according to a change of a digital logic characteristic, includes a comparator for comparing an up/down control signal to a reference signal in disabling either one of the level up shifter or the level down shifter according to the up/down control signal, a level up shifter unit for leveling up of an input voltage in response to a level up shifter/level down shifter disable signal from the comparator, a level down shifter unit for leveling down of an input voltage in response to a level up shifter/level down shifter disable signal from the comparator; and an analog multiplexer for selectively providing a leveled up signal or a leveled down signal from the level up shifter unit or the level down shifter unit.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 4380710 (1983-04-01), Cohen et al.
patent: 4504747 (1985-03-01), Smith et al.
patent: 5332935 (1994-07-01), Shyu
patent: 5341047 (1994-08-01), Rosenthal
patent: 5723986 (1998-03-01), Nakashiro et al.
patent: 5739700 (1998-04-01), Martin
patent: 5892371 (1999-04-01), Maley
patent: 5929656 (1999-07-01), Pagones
patent: 6023175 (2000-02-01), Nunomiya et al.
Chang Daniel D.
Fleshner & Kim LLP
Hyundai Electronics Industries Co,. Ltd.
Tokar Michael
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