Level shifter and buffer circuit

Details Level shifter and buffer circuit Level shifter and buffer circuit

2007-03-27

2007-03-27

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S068000, C326S080000

Reexamination Certificate

active

11142259

ABSTRACT:
A level shifter has a voltage converting circuit converting an input signal provided by a first power supply into an output signal provided by a second power supply, and a reset circuit outputting a reset signal when the first power supply is turned off. The voltage converting circuit has: first and second FETs which are cross-coupled; a first trigger FET connected to the second FET and triggering it in response to the input signal; a second trigger FET connected to the second FET in parallel with the first trigger FET; a third trigger FET connected to the first FET and triggering it in response to an inversion signal of the input signal; and a fourth trigger FET connected to the first FET in parallel with the third trigger FET. Any of the second and the fourth trigger FETs triggers corresponding one of the second FET and the first FET in response to the reset signal.

REFERENCES:
patent: 2003/0179032 (2003-09-01), Kaneko et al.
patent: 2004/0169542 (2004-09-01), Kouzuma
patent: 2001-144600 (2001-05-01), None

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